Sensors

16

Freescale Semiconductor

MMA7450L

CLR_INT1

1: Clear “INT1” and LDX/LDY/LDZ or PDX/PDY/PDZ bits in “Detection source” register depending on “Detection control” reg-

ister setting.

0: Do not clear “INT1” LDX/LDY/LDZ or PDX/PDY/PDZ bits in “Detection source” register.

CLR_INT2

1: Clear “INT2” and LDX/LDY/LDZ or PDX/PDY/PDZ bits in “Detection source” register depending on “Detection control” reg-

ister setting.

0: Do not clear “INT2” and LDX/LDY/LDZ or PDX/PDY/PDZ bits in “Detection source” register.

INTPIN

0: INT1 pin is routed to “INT1” register and INT2 pin is routed to “INT2” register.

1: INT2 pin is routed to “INT1” register and INT1 pin is routed to “INT2” register.

Note: Assigned to single pulse detection even if double

pulse detection is selected. “Double pulse detection se-

zero. When double pulse detection is selected, INT1 reg-

ister bit is not able to be cleared by setting CLR_INT1 bit.

It’s cleared by setting CLR_INT2 bit. In this case, setting

CLR_INT2 clears both INT1 and INT2 register bits and re-

set detecting operation itself.

XDA

1: X axis is disabled for detection.

0: X axis is enabled for detection.

YDA

1: Y axis is disabled for detection.

0: Y axis is enabled for detection.

ZDA

1: Z axis is disabled for detection.

0: Z axis is enabled for detection.

THOPT (This bit is valid for level detection only, not valid

for pulse detection)

0: Threshold value is absolute only

1: Positive/Negative threshold value is available.

DFBW

0: Digital filter band width is 62.5 Hz

1: Digital filter band width is 125 Hz

LDPOL

0: Level detection polarity is positive and detecting condi-

tion is OR 3 axes.

1: Level detection polarity is negative detecting condition

is AND 3 axes.

PDPOL

0: Pulse detection polarity is positive and detecting condi-

tion is OR 3 axes.

1: Pulse detection polarity is negative and detecting con-

dition is AND 3 axes.

DRVO

0: Standard drive strength on SDA/SDO pin

1: Strong drive strength on SDA/SDO pin

$17: Interrupt latch reset (Read/Write

D7

D6

D5

D4

D3

D2

D1

D0

Bit

--

--

--

--

--

--

CLR_INT2 CLR_INT1

Function

0

0

0

0

0

0

0

0

Default

$18: Control 1 (Read/Write)

D7

D6

D5

D4

D3

D2

D1

D0

Bit

DFBW

THOPT

ZDA

YDA

XDA

INTREG[1]

INTREG[0]

INTPIN

Function

0

0

0

0

0

0

0

0

Default

INTREG[1:0]

“INT1” register bit

“INT2” register bit

00

Level Detection

Pulse Detection

01

Pulse Detection

Level Detection

10

Single pulse detection (*Note)

Pulse Detection

$19: Control 2 (Read/Write)

D7

D6

D5

D4

D3

D2

D1

D0

Bit

--

--

--

--

--

DRVO

PDPL

LDPL

Function

0

0

0

0

0

0

0

0

Default