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MSC8144 Datasheet(PDF) 41 Page - Freescale Semiconductor, Inc |
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MSC8144 Datasheet(HTML) 41 Page - Freescale Semiconductor, Inc |
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41 / 80 page ![]() Electrical Characteristics MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 1 Freescale Semiconductor 41 Figure 9 shows the DDR SDRAM output timing for the MCK to MDQS skew measurement (tDDKHMH). Figure 10 shows the DDR SDRAM output timing diagram. Figure 9. Timing for tDDKHMH Figure 10. DDR SDRAM Output Timing MDQS MCK[n] MCK[n] tMCK tDDKHMHmax) = 0.6 ns tDDKHMH(min) = –0.6 ns MDQS ADDR/CMD tDDKHAS, tDDKHCS tDDKHMH tDDKLDS tDDKHDS MDQ[x] MDQS[n] MCK[n] MCK[n] tMCK tDDKLDX tDDKHDX D1 D0 tDDKHAX ,tDDKHCX Write A0 NOOP tDDKHME tDDKHMP |
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