DSP56371 datasheet(4/68 Pages) FREESCALE

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DSP56371 Data Sheet, Rev. 4.1

DSP56371 Overview

Freescale Semiconductor

slave. I2S, left justified, right justified, Sony, AC97, network and other programmable

protocols

— Enhanced Serial Audio Interface I (ESAI_1): up to 4 receivers and up to 6 transmitters, master

or slave. I2S, left justified, right justified, Sony, AC97, network and other programmable

protocols

— Serial Host Interface (SHI): SPI and I2C protocols, multi master capability in I2C mode,

10-word receive FIFO, support for 8, 16 and 24-bit words

— Triple Timer module (TEC).

— 11 dedicated GPIO pins

— Digital Audio Transmitter (DAX): 1 serial transmitter capable of supporting the SPDIF,

IEC958, CP-340 and AES/EBU digital audio formats

— Pins of unused peripherals (except SHI) may be programmed as GPIO lines

2.3

DSP56371 Audio Processor Architecture

This section defines the DSP56371 audio processor architecture. The audio processor is composed of the

following units:

•

The DSP56300 core is composed of the Data ALU, Address Generation Unit, Program Controller,

DMA Controller, Memory Module Interface, Peripheral Module Interface and the On-Chip

Emulator (OnCE). The DSP56300 core is described in the document <st-blue>DSP56300 24-Bit

Digital Signal Processor Family Manual, Motorola publication DSP56300FM/AD.

•

Phased Lock Loop and Clock Generator

•

Memory modules

•

Peripheral modules. The peripheral modules are defined in the following sections.

Memory sizes in the block diagram are defaults. Memory may be differently partitioned, according to the

memory mode of the chip. See Section 2.4.7 On-Chip Memory for more details about memory size.

2.4

DSP56300 Core Functional Blocks

The DSP56300 core provides the following functional blocks:

•

Data arithmetic logic unit (Data ALU)

•

Address generation unit (AGU)

•

Program control unit (PCU)

•

DMA controller (with six channels)

•

Instruction patch controller

•

PLL-based clock oscillator

•

OnCE module

•

Memory

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