DSP56852 datasheet(9/48 Pages) FREESCALE

9 / 48 page

Introduction

56852 Technical Data, Rev. 8

Freescale Semiconductor

Part 3 Signals and Package Information

All digital inputs have a weak internal pull-up circuit associated with them. These pull-up circuits are

enabled by default. Exceptions:

1. When a pin has GPIO functionality, the pull-up may be disabled under software control.

2. Mode pins D13, D14 and D15 have no pull-up.

3. TCK has a weak pull-down circuit always active.

4. Bidirectional I/O pullups automatically disable when the output is enabled.

This table is presented consistently with the Signals Identified by Functional Group figure.

1. BOLD entries in the Type column represents the state of the pin just out of reset.

2. Ouput(Z) means an output in a High-Z condition.

Table 3-1. 56852 Signal and Package Information for the 81-pin MAPBGA

Pin No.

Signal Name

Type

Description

VDD

Logic Power —These pins provide power to the internal structures of

the chip, and should all be attached to VDD.

VDD

VSS

Logic Power - GND—These pins provide grounding for the internal

structures of the chip and should all be attached to VSS.

VSS

VDDIO

I/O Power —These pins provide power for all I/O and ESD structures of

the chip, and should all be attached to VDDIO.

VDDIO

VSSIO

I/O Power - GND—These pins provide grounding for all I/O and ESD

structures of the chip and should all be attached to VSS.

VSSIO

VDDA

Analog Power—These pins supply an analog power source

VSSA

Analog Ground—This pin supplies an analog ground.

DSP56852 Datasheet(PDF) 9 Page - Freescale Semiconductor, Inc