Philips Semiconductors

Product specification

TrenchMOS

™ transistor

PHT6N03T

Standard level FET

GENERAL DESCRIPTION

QUICK REFERENCE DATA

N-channel

enhancement

mode

SYMBOL

PARAMETER

MAX.

UNIT

standard level field-effect power

transistor in a plastic envelope

V

DS

Drain-source voltage

30

V

suitable for surface mounting. Using

I

D

Drain current (DC) T

12.8

A

’trench’

technology,

the

device

Drain current (DC) T

5.9

A

features very low on-state resistance

P

tot

Total power dissipation

8.3

W

and has integral zener diodes giving

T

j

Junction temperature

150

˚C

ESD protection up to 2kV. It is

R

DS(ON)

Drain-source on-state

30

m

Ω

intended

for

use

in

DC-DC

resistance

V

converters and general purpose

switching applications.

PINNING - SOT223

PIN CONFIGURATION

SYMBOL

PIN

DESCRIPTION

1

gate

2

drain

3

source

4

drain (tab)

LIMITING VALUES

Limiting values in accordance with the Absolute Maximum System (IEC 134)

SYMBOL

PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

V

DS

Drain-source voltage

-

-

30

V

V

DGR

Drain-gate voltage

R

-30

V

±V

GS

Gate-source voltage

-

-

16

V

I

D

Drain current (DC)

T

-

12.8

A

T

-

5.9

A

I

D

Drain current (DC)

T

-

9

A

T

-

4.1

A

I

DM

Drain current (pulse peak value)

T

-

51.2

A

T

-

23.6

A

P

tot

Total power dissipation

T

-

8.3

W

T

-

1.8

W

T

Storage & operating temperature

-

- 55

150

˚C

THERMAL RESISTANCES

SYMBOL

PARAMETER

CONDITIONS

TYP.

MAX.

UNIT

R

th j-sp

Thermal resistance junction to

Mounted on any PCB

12

15

K/W

solder point

R

th j-amb

Thermal resistance junction to

Mounted on PCB of Fig.19

-

70

K/W

ambient

d

g

s

4

1

23

November 1997

1

Rev 1.200