AD9865BCPRL datasheet(26/48 Pages) AD

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AD9865

Rev. A | Page 26 of 48

6-BIT DIGITAL WORD-DECIMAL EQUIVALENT

–12

–6

612

Figure 56. Digital Gain Mapping of RxPGA

Table 15. SPI Registers RxPGA Control

Address

(Hex)

Bit

Description

0x09

(6)

Enable RxPGA update via SPI

(5:0)

RxPGA gain code

0x0B

(6)

Select TxPGA via PGA[5:0]

(5)

Select RxPGA via PGA[5:0]

(3)

Enable software GAIN strobe – Full-duplex

(2)

Enable RxPGA update via Tx[5:0] – Full-duplex

(1)

3-bit RxPGA gain mapping – Half-duplex

The RxPGA gain register can be updated via the Tx[5:0] port,

the PGA[5:0] port, or the SPI port. The first two methods allow

fast updates of the RxPGA gain register and should be

considered for digital AGC functions requiring a fast closed-

loop response. The SPI port allows direct update and readback

of the RxPGA gain register via Register 0x09 with an update

rate limited to 1.6 MSPS (with SCLK = 32 MHz). Note that Bit 6

of Register 0x09 must be set for a read or write operation.

Updating the RxPGA via the Tx[5:0] port is an option only in

full-duplex mode1. In this case, a high level on the GAIN pin,2

with TXSYNC low, programs the PGA setting on either the

rising edge or falling edge of RXCLK, as shown in Figure 57.

The GAIN pin must be held high, TXSYNC must be held low,

and GAIN data must be stable for one or more clock cycles to

update the RxPGA gain setting.

A low level on the GAIN pin enables data to be fed to the digital

interpolation filter. This interface should be considered when

upgrading existing designs from the AD9875/AD9876 MxFE

products or half-duplex applications trying to minimize an

ASIC’s pin count.

RXCLK

Tx SYNC

Tx [5:0]

GAIN

Figure 57. Updating RxPGA via Tx[5:0] in Full-Duplex Mode

Updating the RxPGA (or TxPGA) via the PGA[5:0] port is an

option for both the half-duplex3 and full-duplex interface. The

PGA port consists of an input buffer that passes the 6-bit data

appearing at its input directly to the RxPGA (or TxPGA) gain

RxPGA or TxPGA gain register. In applications that switch

between RxPGA and TxPGA gain control via PGA[5:0], be

careful that the RxPGA (or TxPGA) is not inadvertently loaded

with the wrong data during a transition. In the case of an

RxPGA to TxPGA transition, first deselect the RxPGA gain

setting, and then select the TxPGA gain register.

The RxPGA also offers an alternative 3-bit word gain mapping

option4 that provides a −12 dB to +36 dB span in 8 dB increments

as shown in Table 16. The 3-bit word is directed to PGA[5:3]

with PGA[5] being the MSB. This feature is backward-compatible

with the AD9975 MxFE and allows direct interfacing to the

CX11647 or INT5130 HomePlug 1.0 PHYs.

Table 16. PGA Timing for AD9975 Backward-Compatible

Mode

Digital Gain Setting

PGA[5:3]

Decimal

Gain (dB)

000

−12

001

−12

010

−4

011

100

101

110

111

1 Default setting for full-duplex mode (MODE = 1).

2 The GAIN strobe can also be set in software via Reg. 0x0B, Bit 3 for

continuous updating. This eliminates the requirement for external GAIN

signal, reducing the ASIC pin count by 1.

3 Default setting for half-duplex mode (MODE = 0).

4 Default setting for MODE = 0 and CONFIG =1.

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