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56F8013 Datasheet(PDF) 49 Page - Freescale Semiconductor, Inc |
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56F8013 Datasheet(HTML) 49 Page - Freescale Semiconductor, Inc |
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49 / 125 page  Register Descriptions 56F8013/56F8011 Data Sheet, Rev. 10 Freescale Semiconductor 49 Preliminary 5.6.1.1 LVI IPL—Bits 15–14 This field is used to set the interrupt priority levels for a peripheral IRQ. This IRQ is limited to priorities 0 through 2 and is disabled by default. • 00 = IRQ disabled (default) • 01 = IRQ is priority level 0 • 10 = IRQ is priority level 1 • 11 = IRQ is priority level 2 5.6.1.2 Reserved—Bits 13–10 This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing. 5.6.1.3 EOnCE Receive Register Full Interrupt Priority Level (RX_REG IPL)— Bits 9–8 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 1 through 3. It is disabled by default. • 00 = IRQ disabled (default) • 01 = IRQ is priority level 1 • 10 = IRQ is priority level 2 • 11 = IRQ is priority level 3 5.6.1.4 EOnCE Transmit Register Empty Interrupt Priority Level (TX_REG IPL)— Bits 7–6 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 1 through 3. It is disabled by default. • 00 = IRQ disabled (default) • 01 = IRQ is priority level 1 • 10 = IRQ is priority level 2 • 11 = IRQ is priority level 3 5.6.1.5 EOnCE Trace Buffer Interrupt Priority Level (TRBUF IPL)— Bits 5–4 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 1 through 3. It is disabled by default. • 00 = IRQ disabled (default) • 01 = IRQ is priority level 1 • 10 = IRQ is priority level 2 • 11 = IRQ is priority level 3 |
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