56F8345 datasheet(38/164 Pages) FREESCALE

38 / 164 page

56F8345 Technical Data, Rev. 17

Freescale Semiconductor

Preliminary

Figure 3-3 Connecting a Ceramic Resonator

Note:

The OCCS_COHL bit must be set to 0 when a ceramic resonator is used. The reset condition on the

OCCS_COHL bit is 0. Please see the COHL bit in the Oscillator Control (OSCTL) register, discussed

in the 56F8300 Peripheral User’s Manual.

3.2.3

External Clock Source

The recommended method of connecting an external clock is illustrated in Figure 3-4. The external clock

source is connected to XTAL and the EXTAL pin is grounded. Set OCCS_COHL bit high when using an

external clock source as well.

Figure 3-4 Connecting an External Clock Signal Register

3.3 Registers

When referring to the register definitions for the OCCS in the 56F8300 Peripheral User Manual, use the

NOT contain this oscillator.

Part 4 Memory Map

4.1 Introduction

The 56F8345 and 56F8145 devices are 16-bit motor-control chips based on the 56800E core. These parts

use a Harvard-style architecture with two independent memory spaces for Data and Program. On-chip

EXTAL XTAL

Sample External Ceramic Resonator Parameters:

Rz = 750 KΩ

EXTAL XTAL

CL1

CL2

Resonator Frequency = 4 - 8MHz (optimized for 8MHz)

3 Terminal

2 Terminal

CLKMODE = 0

XTAL

EXTAL

External

VSS

Clock

Note: When using an external clocking

source with this configuration, the input

“CLKMODE” should be high and COHL bit in

the OSCTL register should be set to 1.

56F8345 Datasheet(PDF) 38 Page - Freescale Semiconductor, Inc