56F8345 datasheet(17/164 Pages) FREESCALE

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Introduction

56F8345 Technical Data, Rev. 17

Freescale Semiconductor

Preliminary

Part 2 Signal/Connection Descriptions

2.1 Introduction

The input and output signals of the 56F8345 and 56F8145 are organized into functional groups, as detailed

in Table 2-1 and as illustrated in Figure 2-1. In Table 2-2, each table row describes the signal or signals

present on a pin.

Table 2-1 Functional Group Pin Allocations

Functional Group

Number of Pins in Package

56F8345

56F8145

Power (VDD or VDDA)

Power Option Control

Ground (VSS or VSSA)

Supply Capacitors1 & VPP

1. If the on-chip regulator is disabled, the VCAP pins serve as 2.5V VDD_CORE power inputs

PLL and Clock

Bus Control

Interrupt and Program Control

Pulse Width Modulator (PWM) Ports

Serial Peripheral Interface (SPI) Port 0

Serial Peripheral Interface (SPI) Port 1

—4

Quadrature Decoder Port 02

2. Alternately, can function as Quad Timer pins or GPIO

Quadrature Decoder Port 13

3. Pins in this section can function as Quad Timer, SPI 1, orGPIO

4—

Serial Communications Interface (SCI) Ports

CAN Ports

2—

Analog-to-Digital Converter (ADC) Ports

Timer Module Ports

JTAG/Enhanced On-Chip Emulation (EOnCE)

Temperature Sense

1—

Dedicated GPIO ( Address Bus = 11; Data Bus = 44)

4. EMI not functional in these packages; use as GPIO pins.

Note: See Table 1-1 for 56F8145 functional differences.

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