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MPC860DP Datasheet(PDF) 23 Page - Freescale Semiconductor, Inc |
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MPC860DP Datasheet(HTML) 23 Page - Freescale Semiconductor, Inc |
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23 / 80 page  MPC860 Family Hardware Specifications, Rev. 7 Freescale Semiconductor 23 Bus Signal Timing Figure 7. Input Data Timing in Normal Case Figure 8 provides the timing for the input data controlled by the UPM for data beats where DLT3 = 1 in the UPM RAM words. (This is only the case where data is latched on the falling edge of CLKOUT.) Figure 8. Input Data Timing when Controlled by UPM in the Memory Controller and DLT3 = 1 Figure 9 through Figure 12 provide the timing for the external bus read controlled by various GPCM factors. CLKOUT TA D[0:31], DP[0:3] B16 B17 B19 B18 CLKOUT TA D[0:31], DP[0:3] B20 B21 |
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