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MPC860DP Datasheet(PDF) 20 Page - Freescale Semiconductor, Inc

Part # MPC860DP
Description  Hardware Specifications
PDF  80 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC860DP Datasheet(HTML) 20 Page - Freescale Semiconductor, Inc

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MPC860 Family Hardware Specifications, Rev. 7
20
Freescale Semiconductor
Bus Signal Timing
Figure 2 is the control timing diagram.
Figure 2. Control Timing
Figure 3 provides the timing for the external clock.
8
The timing B30 refers to CS when ACS = 00 and to WE(0:3) when CSNT = 0.
9
The signal UPWAIT is considered asynchronous to the CLKOUT and synchronized internally. The timings specified
in B37 and B38 are specified to enable the freeze of the UPM output signals as described in Figure 17.
10 The AS signal is considered asynchronous to the CLKOUT. The timing B39 is specified in order to allow the behavior
specified in Figure 20.
CLKOUT
Outputs
A
B
2.0 V
0.8 V
0.8 V
2.0 V
2.0 V
0.8 V
2.0 V
0.8 V
Outputs
2.0 V
0.8 V
2.0 V
0.8 V
B
A
Inputs
2.0 V
0.8 V
2.0 V
0.8 V
D
C
Inputs
2.0 V
0.8 V
2.0 V
0.8 V
C
D
A
Maximum output delay specification
B
Minimum output hold time
C
Minimum input setup time specification
D
Minimum input hold time specification



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