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© Andigilog, Inc. 2005
www.andigilog.com
April 2006 - 70A03204
aTS75
Figure 8. Pointer set followed by immediate read from a 2-byte register (Temperature, TOS, or THYST Register)
0
0
0
0
0
0
P1
P0
A2
A1
A0
Address Byte
Pointer Byte
1
1
0
0
R/W
S
A
A
Ack
from
aTS75
Ack
from
aTS75
....
Note: This segment of this timing diagram is a generic
pointer set cycle which must be followed by either an
immediate read cycle or write cycle as shown in this
figure and in figures 10, 11, and 12.
SCL
SDA
Most Significant Data
Byte
(from aTS75)
Least Significant Data Byte
(from aTS75)
D7
D6
D5
D4
D3
D2
D1
D0
A2
A1
A0
D7
D6
D5
D4
0
0
0
0
Address Byte
1
1
0
0
R/W
S
P
A
A
N
Ack
from
aTS75
Ack
from
Master
No Ack
from
Master
Repeat
Start
from
...
SCL
SDA
Figure 9. Two-byte read from preset pointer location (Temperature, TOS, or THYST Register)
D7
D6
D5
D4
D3
D2
D1
D0
A2
A1
A0
D7
D6
D5
D4
0
0
0
0
Address
Byte
Most Significant Data
Byte
(from aTS75)
1
1
0
0
R/W
Least Significant Data
Byte
(from aTS75)
S
P
A
A
N
Ack
from
aTS75
Ack
from
Master
No Ack
from
Master
SCL
SDA
Figure 10 . One-byte read from Configuration Register with preset pointer
X
D6
D5
D4
D3
D2
D1
D0
A2
A1
A0
Address Byte
Data Byte
(from aTS75)
1
1
0
0
R/W
S
P
A
N
Ack
from
aTS75
No Ack
from
Master
SCL
SDA
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