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© Andigilog, Inc. 2005
www.andigilog.com
April 2006 - 70A03204
aTS75
Figure 11. Pointer set followed by immediate write to a 2-byte register (TOS or THYST Register)
SCL
A
Ack
from
aTS75
0
0
0
0
0
0
P1
P0
A2
A1
A0
Address Byte
Pointer Byte
1
1
0
0
R/W
S
A
Ack
from
aTS75
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
0
0
0
0
Most Significant Data Byte
(from Master)
Least Significant Data Byte
(from Master)
P
A
A
Ack
from
aTS75
Ack
from
aTS75
....
....
A
SDA
Figure 12. Pointer set followed by immediate read from Configuration Register
A2
A1
A0
Address Byte
1
1
0
0
R/W
S
Repeat Start
from
Master
0
0
0
0
0
0
P1
P0
A2
A1
A0
Address Byte
Pointer Byte
1
1
0
0
R/W
S
A
A
Ack
from
aTS75
Ack
from
aTS75
A2
A1
A0
Address Byte
(repeated here for
clairity,
transmitted only once
in the actual sequence)
1
0
R/W
A
Ack
from
aTS75
X
D6
D5
D4
D3
D2
D1
D0
Data Byte
(from aTS75)
P
N
No Ack
from
Master
1
0
SCL
A
SD
....
Figure 13. Pointer set followed by immediate write to the Configuration Register
Data Byte
(from Master)
Address Byte
X
D6
D5
D4
D3
D2
D1
D0
P
A
Ack
from
aTS75
0
0
0
0
0
0
P1
P0
A2
A1
A0
Pointer Byte
1
1
0
0
R/W
S
A
A
Ack
from
aTS75
Ack
from
aTS75
SCL
SDA