XRT86VL32IB datasheet(19/174 Pages) EXAR

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XRT86VL32

REV. V1.2.0

DUAL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION

5-4

CAS MF Align

Sel[1:0]

R/W

CAS Multiframe Alignment Declaration Algorithm Select[1:0]

These bits allow the user to select which CAS Multiframe Alignment Decla-

ration algorithm the Receive E1 Framer block will employ, according to the

table below.

NOTE: For information on the criteria that the Receive E1 Framer block

uses in order to declare the “Loss of CAS Multiframe” defect

condition, please see register description for the Framing Control

TABLE 4: FRAMING SELECT REGISTER (FSR)

HEX ADDRESS: 0Xn107

BIT

FUNCTION

TYPE

DEFAULT

DESCRIPTION-OPERATION

CAS MF

ALIGN

SEL[1:0]

CAS MULTIFRAME ALIGNMENT DECLARATION ALGORITHM

SELECTED

00/11

CAS Multiframe Alignment is Disabled

The “16-Frame” Algorithm

If this alignment algorithm is selected, then the Receive

E1 Framer block will monitor the 16th timeslot of each

incoming E1 frame and will declare CAS Multiframe align-

ment (e.g., clear the Loss of CAS Multiframe” defect) con-

dition; anytime that it detects 15 consecutive E1 frames in

which bits 1 - 4 (of timeslot 16) do not contain the “CAS

Multiframe Alignment” pattern; which is immediately fol-

lowed by an E1 frame that DOES contain the “CAS Multi-

frame Alignment” pattern.

The “2-Frame” (ITU-T G.732) Algorithm

If this alignment algorithm is selected, then the Receive

E1 Framer block will monitor the 16th timeslot of each

incoming E1 frame and will declare CAS Multiframe align-

ment (e.g., clear the Loss of CAS Multiframe” defect) con-

dition; anytime that it detects a single E1 frame in which

bits 1 - 4 (of timeslot 16) do not contain the “CAS Multi-

frame Alignment” pattern; which is immediately followed

by an E1 frame that DOES contain the “CAS Multiframe

Alignment” pattern.

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