XRT86VL32IB datasheet(45/174 Pages) EXAR

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XRT86VL32

REV. V1.2.0

DUAL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION

TABLE 21: DMA 0 (WRITE) CONFIGURATION REGISTER (D0WCR)

HEX ADDRESS: 0Xn118

BIT

FUNCTION

TYPE

DEFAULT

DESCRIPTION-OPERATION

DMA0 RST

R/W

DMA_0 Reset

This bit resets the transmit DMA (Write) channel 0.

0 = Normal operation.

1 = A zero to one transition resets the transmit DMA (Write) channel 0.

DMA0 ENB

R/W

DMA_0 Enable

This bit enables the transmit DMA_0 (Write) interface. After a transmit

DMA is enabled, DMA transfers are only requested when the transmit

buffer status bits indicate that there is space for a complete message

or cell.

The DMA write channel is used by the external DMA controller to

transfer data from the external memory to the HDLC buffers within the

E1 Framer. The DMA Write cycle starts by E1 Framer asserting the

DMA Request (REQ0) ‘low’, then the external DMA controller should

drive the DMA Acknowledge (ACK0) ‘low’ to indicate that it is ready to

start the transfer. The external DMA controller should place new data

on the Microprocessor data bus each time the Write Signal is Strobed

low if the WR is configured as a Write Strobe. If WR is configured as a

direction signal, then the external DMA controller would place new

data on the Microprocessor data bus each time the Read Signal (RD)

is Strobed low.

0 = Disables the transmit DMA_0 (Write) interface

1 = Enables the transmit DMA_0 (Write) interface

WR TYPE

R/W

Write Type Select

This bit selects the function of the WR signal.

0 = WR functions as a direction signal (indicates whether the current

bus cycle is a read or write operation) and RD functions as a data

strobe signal.

1 =WR functions as a write strobe signal

4 - 3 Reserved

Reserved

DMA0_CHAN(2)

R/W

Channel Select

These three bits select which T/E1 channel within the XRT86VL32

uses the Transmit DMA_0 (Write) interface.

000 = Channel 0

001 = Reserved

001 = Channel 2

011 = Reserved

1xx = Reserved

DMA0_CHAN(1)

R/W

DMA0_CHAN(0)

R/W

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