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SP6122 Datasheet(PDF) 16 Page - Sipex Corporation |
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SP6122 Datasheet(HTML) 16 Page - Sipex Corporation |
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16 / 19 page  16 Date: 10/02/04 SP6122 Low Voltage, Micro 8, PFET, Buck Controller © Copyright 2004 Sipex Corporation RDS(ON) OVER CURRENT PROTECTION Fault conditions are detected via an over voltage condition across the PMOS switch during conduction. This is commonly known as RDS(ON) sensing. RDS(ON) sensing is inac- curate but efficient and is used where an indicator of over current behavior is required for protection. Two advanced features are incorporated in the SP6122 RDS(ON) sensing scheme. The sensing environment is very noisy. Typical schemes require some exter- nal filtering in order to avoid spurious faults due to noise or load transients, often com- promising the protection and performance at low duty ratios. The SP6122 incorporates a 10µs internal sample and hold filter after the main sense comparator. In this fashion, small pulse widths can be detected while maintaining adequate filtering against false glitches. In addition, temperature compen- sation is added such that the over current detection threshold at any temperature can be calculated with reasonable accuracy at room temperature. For our evaluation board example: ITRIP = (150mV + ISETRSET)/RDS(ON)= (150mV + 20µA*1kΩ)/25mΩ = 6.8A This is the about the same trip threshold at room, hot or cold because a temperature coefficient has been added to both the 150mV and the 20µA set currents. This temperature coefficient tracks the 25mΩ RDS(ON) of the external FET. Due to the small size of these power supplies, thermal coupling exists be- tween the PFET and the SP6122, making this thermal compensation reasonable, but not perfect. Notice there is about a 50% pad between the maximum usable current (5A) and the over current trip threshold (7A) in order to accommodate PFET and overall system variation. Layout Guidelines PCB layout plays a critical role in proper function of the converters and EMI control. In switch mode power supplies, loops carry- ing high di/dt give rise to EMI and ground bounce. The goal of layout optimization is to identify these loops and minimize them. It is also crucial on how to connect the controller ground such that its operation is not affected by noise. The following guidelines should be followed to ensure proper operation. 1. A ground plane is recommended for minimizing noises, copper losses and maximizing heat dissipation. 2. Connect the ground of the feedback divider to the GND pin of the IC. Then connect this pin as close as possible to the ground of the output capacitor. 3. The Vcc bypass capacitor should be right next to the Vcc and GND pins. 4. The traces connecting to the feedback resistors and current sense components should be short and far away from the switch node and switching components. 5. Minimize the trace length/maximize the trace width between the PDRV pin and the gate of the PMOS. 6. Minimize the loop composed of input capacitors, PMOS and Schottky diode, as this loop carries high di/dt current. Also increase the trace width to reduce copper losses. 7. Maximize the trace width of the loop connecting the inductor, output capaci- tors, and Schottky diode. 8. For an layout example of an SP6122 power supply (3.3Vin and 1.9Vout at 4A) see the SP6122 Evaluation Board Manual. Features and Protection: continued |
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