SAA7183A datasheet(13/45 Pages) PHILIPS

13 / 45 page

1996 Oct 02

Philips Semiconductors

Preliminary speciﬁcation

Digital Video Encoder (EURO-DENC2)

SAA7182A; SAA7183A

Output interface/DACs

In the output interface encoded both Y and C signals are

converted from digital-to-analog in 10-bit resolution.

Y and C signals are also combined to a 10-bit CVBS

signal.

The CVBS output occurs with the same processing delay

as the Y and C outputs. Absolute amplitudes at the input

of the DAC for CVBS is reduced by 15

⁄16 with respect to

Y and C DACs to make maximum use of conversion

ranges.

RED, GREEN and BLUE signals are also converted from

digital-to-analog, each providing a 9-bit resolution. It is

also possible to feed through three external analog RGB

signals at pins RI, BI and GI when pin SELI = HIGH

Outputs of the DACs can be set together in two groups via

software control to minimum output voltage for either

purpose.

Synchronization

Synchronization of the EURO-DENC2 is able to operate in

two modes; slave mode and master mode.

In the slave mode, the circuit accepts synchronization

pulses at the bidirectional RCV1 port. The timing and

trigger behaviour related to RCV1 can be influenced by

programming the polarity and on-chip delay of RCV1.

Active slope of RCV1 defines the vertical phase and

optionally the odd/even and colour frame phase to be

initialized, it can be also used to set the horizontal phase.

If the horizontal phase is not to be influenced by RCV1, a

horizontal pulse needs to be supplied at the RCV2 pin.

Timing and trigger behaviour can also be influenced for

RCV2.

If there are missing pulses at RCV1 and/or RCV2, the time

base of EURO-DENC2 runs free, thus an arbitrary number

of synchronization slopes may miss, but no additional

pulses (with the incorrect phase) must occur.

If the vertical and horizontal phase is derived from RCV1,

RCV2 can be used for horizontal or composite blanking

input or output.

Alternatively, the device can be triggered by auxiliary

codes in a

CCIR 656 data stream at the MP port

In the master mode, the time base of the circuit

continuously runs free. On the RCV1 port, the IC can

output:

• A Vertical Sync signal (VS) with 3 or 2.5 lines duration,

or;

• An ODD/EVEN signal which is LOW in odd fields, or;

• A field sequence signal (FSEQ) which is HIGH in the first

of 4, 8, 12 fields respectively.

On the RCV2 port, the IC can provide a horizontal pulse

with programmable start and stop phase; this pulse can be

inhibited in the vertical blanking period to build up, for

example, a composite blanking signal.

The polarity of both RCV1 and RCV2 is selectable by

software control.

The length of a field and the start and end of its active part

can be programmed. The active part of a field always

starts at the beginning of a line.

I2C-bus interface

The I2C-bus interface is a standard slave transceiver,

supporting 7-bit slave addresses and 400 kbits/s

guaranteed transfer rate. It uses 8-bit subaddressing with

an auto-increment function. All registers are write only,

except one readable status byte.

Two I2C-bus slave addresses are selected:

88H: LOW at pin SA

8CH: HIGH at pin SA.

Input levels and formats

EURO-DENC2 expects digital Y, Cb, Cr data with levels

(digital codes) in accordance with

“CCIR 601”.

For C and CVBS outputs, deviating amplitudes of the

colour difference signals can be compensated by

independent gain control setting, while gain for luminance

is set to predefined values, distinguishable for 7.5 IRE

set-up or without set-up.

For RGB outputs variable amplification of the Y, Cb and Cr

components is provided, enabling adjustment of contrast

and colour saturation in certain range.

Reference levels are measured with a colour bar,

100% white, 100% amplitude and 100% saturation.

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