SAA7183A datasheet(34/45 Pages) PHILIPS

34 / 45 page

1996 Oct 02

Philips Semiconductors

Preliminary speciﬁcation

Digital Video Encoder (EURO-DENC2)

SAA7182A; SAA7183A

CHARACTERISTICS

VDDD(3) = 3.0 to 3.6 V; VDDD(5) = 4.75 to 5.25 V; Tamb =0to+70 °C; unless otherwise speciﬁed.

SYMBOL

PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

Supply

VDDA(3)

analog supply voltage (3.3 V)

3.1

3.5

VDDD(3)

digital supply voltage (3.3 V)

3.0

3.6

VDDD(5)

digital supply voltage (5 V)

4.75

5.25

IDDA

analog supply current

note 1

−

110

IDDD(3)

digital supply current (3.3 V)

note 1

−

IDDD(5)

digital supply current (5 V)

note 1

−

Inputs

VIL

LOW level input voltage

(except SDA, SCL, AP, SP and XTALI)

−0.5

+0.8

VIH

HIGH level input voltage

(except LLC, SDA, SCL, AP, SP and XTALI)

2.0

VDDD(5) + 0.5 V

HIGH level input voltage (LLC)

2.4

VDDD(5) + 0.5 V

ILI

input leakage current

−

µA

input capacitance

clocks

−

data

−

8pF

I/Os at high impedance

−

8pF

Outputs

VOL

LOW level output voltage

(except SDA and XTALO)

note 2

0.6

VOH

HIGH level output voltage

(except LLC, SDA, and XTALO)

note 2

2.4

VDDD(5) + 0.5 V

HIGH level output voltage (LLC)

note 2

2.6

VDDD(5) + 0.5 V

I2C-bus; SDA and SCL

VIL

LOW level input voltage

−0.5

+1.5

VIH

HIGH level input voltage

3.0

VDDD(5) + 0.5 V

input current

Vi = LOW or HIGH

−10

+10

µA

VOL

LOW level output voltage (SDA)

IOL =3mA

−

0.4

output current

during acknowledge

−

Clock timing (LLC)

TLLC

cycle time

note 3

duty factor tHIGH/TLLC

note 4

rise time

note 3

−

5ns

fall time

note 3

−

6ns

Input timing

tSU;DAT

input data set-up time (any other except

CDIR, SCL, SDA, RESET, AP and SP)

−

tHD;DAT

input data hold time (any other except

CDIR, SCL, SDA, RESET, AP and SP)

−

SAA7183A Datasheet(PDF) 34 Page - NXP Semiconductors

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