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SN74LVC166A Datasheet(PDF) 7 Page - Texas Instruments

Part # SN74LVC166A
Description  SN74LVC166A 8-Bit Parallel-Load Shift Registers with Clear
PDF  23 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

SN74LVC166A Datasheet(HTML) 7 Page - Texas Instruments

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5.6 Timing Characteristics (continued)
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
DESCRIPTION
CONDITION
VCC
-40°C to 125°C
UNIT
MIN
MAX
tSU
Setup time
Data before CLK↑
2.5 V ± 0.2 V
4.5
ns
tSU
Setup time
CLR inactive before CLK↑
2.5 V ± 0.2 V
5.9
ns
tH
Hold time
SER data after CLK↑
2.5 V ± 0.2 V
0.5
ns
tH
Hold time
Parallel data after SH/LD↓
2.5 V ± 0.2 V
0
ns
tH
Hold time
SH/LD high after CLK↑
2.5 V ± 0.2 V
0.1
ns
tH
Hold time
CLK INH high after CLK↑
2.5 V ± 0.2 V
0.3
ns
tH
Hold time
Data after CLK↑
2.5 V ± 0.2 V
1.5
ns
tW
Pulse duration
CLR low
3.3 V ± 0.3 V
4.3
ns
tW
Pulse duration
SH/LD low
3.3 V ± 0.3 V
4.3
ns
tW
Pulse duration
CLK
3.3 V ± 0.3 V
4.3
ns
tSU
Setup time
SH/LD high before CLK↑
3.3 V ± 0.3 V
3.5
ns
tSU
Setup time
SER before CLK↑
3.3 V ± 0.3 V
4
ns
tSU
Setup time
CLK INH before CLK↑
3.3 V ± 0.3 V
1
ns
tSU
Setup time
Data before CLK↑
3.3 V ± 0.3 V
2.9
ns
tSU
Setup time
CLR inactive before CLK↑
3.3 V ± 0.3 V
4
ns
tH
Hold time
SER data after CLK↑
3.3 V ± 0.3 V
0.5
ns
tH
Hold time
Parallel data after SH/LD↓
3.3 V ± 0.3 V
0
ns
tH
Hold time
SH/LD high after CLK↑
3.3 V ± 0.3 V
0.2
ns
tH
Hold time
CLK INH high after CLK↑
3.3 V ± 0.3 V
0.5
ns
tH
Hold time
Data after CLK↑
3.3 V ± 0.3 V
1.5
ns
SH/LD
CLK
CLK INH
SER
VCC
H
QH
A, C, E, G held LOW
B, D, F held HIGH
INHIBIT
LOAD
SHIFT
SHIFT
STARTUP
CLR
CLEAR
Figure 5-1. Timing Diagram
www.ti.com
SN74LVC166A
SCLSA15 – MAY 2024
Copyright © 2024 Texas Instruments Incorporated
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