SN74LVC166A 8-Bit Parallel-Load Shift Registers with Clear

1 Features

• Operating range from 1.1V to 3.6V

• Over-voltage tolerant inputs support up to 5.5V

independent of VCC

• Supports partial-power-down with back drive

protection (Ioff)

• High push-pull output drive strength:

– ±24mA at 3.3V

– ±8mA at 2.3V

– ±4mA at 1.65V

• Maximum propagation delay of 11.2ns at 3.3V

supply

• Latch-up performance exceeds 100mA

per JESD78

2 Applications

• Increase the number of inputs on a microcontroller

• Read in board revision

3 Description

The SN74LVC166A contains one 8-bit parallel-load

shift register. Data is loaded synchronously using the

shift or load (SH/LD) select and clock (CLK) inputs.

The device includes a serial (SER) input to allow

for daisy chaining and an asynchronous clear (CLR)

input.

Package Information

PART NUMBER

PACKAGE(1)

PACKAGE SIZE(2)

BODY SIZE (NOM)(3)

SN74LVC166A

BQB (WQFN, 16)

3.5mm × 2.5mm

3.5mm × 2.5mm

D (SOIC, 16)

9.9mm × 6mm

9.9mm × 3.9mm

PW (TSSOP, 16)

5mm × 6.4mm

5mm × 4.4mm

(1)

For more information, see Section 11.

(2)

The package size (length × width) is a nominal value and

includes pins, where applicable

(3)

The body size (length × width) is a nominal value and does

not include pins.

D

Q

R

D

Q

R

SER

SH/LD

CLK INH

CLK

CLR

A

B

C

D

E

F

G

H

5 Additional

Shift Register

Stages

D

Q

R

QH

Functional Diagram

SN74LVC166A

SCLSA15 – MAY 2024

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.