SCN26562 datasheet(4/17 Pages) PHILIPS

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Philips Semiconductors

Product specification

SCN26562

Dual universal serial communications controller (DUSCC)

1995 May 1

BLOCK DIAGRAM

D0–D7

RDYN

RDN

A1–A6

CEN

RESETN

BUS

BUFFER

CHANNEL

MODE AND

TIMING A/B

DPLL CLK

MUX A/B

DPLLA/B

CTCRA/B

CTPRHA/B

CTPRLA/B

RxD A/B

TxD A/B

BRG

COUNTER

TIMER A/B

C/T CLK

MUX A/B

CTHA/B

CTLA/B

TRANS CLK

MUX

TRANSMIT

A/B

TPRA/B

TTRA/B

TX SHIFT

REG

TRANSMIT

4 DEEP

FIFO

CRC

GENERATOR

SPEC CHAR

GEN LOGIC

RCVR CLK

MUX

RCVR

SHIFT REG

RECEIVER

4 DEEP

FIFO

CRC

ACCUM

RECEIVER

A/B

RPRA/B

RTRA/B

S1RA/B

S2RA/B

BISYNC

COMPARE

LOGIC

ADDRESS

DECODE

DMA

CONTROL

INTERFACE/

OPERATION

CONTROL

CCRA/B

PCRA/B

RSRA/B

TRSRA/B

ICTSRA/B

R/W

DECODE

GSR

CMR1A/B

CMR2A/B

OMRA/B

MPU

INTERFACE

WRN

RTxDRQAN/GPO1AN

DMA

INTERFACE

RTxDRQBN/GPO1BN

TxDRQAN/GPO2AN

TxDRQBN/GPO2BN

RTxDAKAN/GPI1AN

RTxDAKBN/GPI1BN

TxDAKAN/GPI2AN

TxDAKBN/GPI2BN

EOPN

TRxCA/B

SPECIAL

FUNCTION

PINS

RTxCA/B

CTSAN/LCAN

CTSBN/LCBN

DCDBN/SYNIBN

DCDAN/SYNIAN

RTSBN/SYNOUTBN

RTSAN/SYNOUTAN

INTERRUPT

CONTROL

ICRA/B

IERA/B

IVR

IVRM

IRQN

IACKN

X1/CLK

OSCILLATOR

DUSCC

LOGIC

SD00204

Figure 2. Block Diagram

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