TDA10021 datasheet(4/16 Pages) PHILIPS

4 / 16 page

2001 Oct 01

Philips Semiconductors

Product speciﬁcation

DVB-C channel receiver

TDA10021HT

PINNING

SYMBOL

TYPE(1)

DESCRIPTION

VDDD18

digital supply voltage for the core (1.8 V typ.)

XIN

XTAL oscillator input pin: a fundamental XTAL oscillator is connected between the

XIN and XOUT pins. The XTAL frequency must be chosen so that the system

frequency SYSCLK (XIN

× multiplying factor of the PLL) equals 1.6 times the tuner

output intermediate frequency; i.e. SYSCLK = 1.6

× IF.

XOUT

XTAL oscillator output pin: a fundamental XTAL oscillator is connected between the

XIN and XOUT pins

VSSD18

digital ground for the core

SACLK

sampling clock: this output clock can be fed to an external 10-bit ADC as the

sampling clock; SACLK = SYSCLK/2

TEST

test input pin: in normal mode, pin TEST must be connected to ground

VDDD18

digital supply voltage for the core (1.8 V typ.)

VSSD18

digital ground for the core

AGCTUN

O/OD

ﬁrst PWM encoded output signal for AGC tuner: this signal is fed to the AGC

ampliﬁer through a single RC network. The maximum signal frequency on the

VAGC output is XIN/16. AGC information is refreshed every 1024 symbols.

IICDIV

IICDIV: this pin allows the frequency of the I2C-bus internal system clock to be

selected, depending on the crystal frequency. The internal I2C-bus clock is a

division of XIN by 4IICDIV.

AGCIF

O/OD

second PWM encoded output signal for the AGC IF: This signal is fed to the AGC

ampliﬁer through a single RC network. The maximum signal frequency on the

VAGC output is XIN/16. AGC information is refreshed every 1024 symbols.

However AGCIF can also be conﬁgured to output a PWM signal, the value of which

can be programmed through the I2C-bus interface.

SADDR

SADDR is the LSB of the I2C-bus address of the TDA10021HT. The MSBs are

internally set to 000110. Therefore the complete I2C-bus address of the

TDA10021HT is (MSB to LSB) 0, 0, 0, 1, 1, 0 and SADDR.

VDDD50

digital supply voltage for the pad 5.0 V (necessary for 5 V tolerant inputs)

VDDD33

digital supply voltage for the pads (3.3 V typ.)

VSSD33

digital ground for the pads

CLR#

the CLR# input is asynchronous and active LOW, and clears the TDA10021HT:

When CLR# goes LOW, the circuit immediately enters its reset mode and normal

operation will resume 4 XIN falling edges after CLR# returns HIGH. The I2C-bus

CLR# at LOW level is 4 XIN clock periods.

SCL

I2C-bus clock input: SCL should nominally be a square wave with a maximum

frequency of 400 kHz. SCL is generated by the system I2C-bus master.

SDA

I/OD

SDA is a bidirectional signal: it is the serial input/output of the I2C-bus internal block.

A pull-up resistor (typically 4.7 k

Ω) must be connected between SDA and VDDD50 for

proper operation (open-drain output).

SDAT

I/OD

SDAT is equivalent to SDA I/O of the TDA10021HT but can be 3-stated by I2C-bus

programming. It is actually the output of a switch controlled by parameter BYPIIC of

external pull-up resistor.

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