2001 Oct 01

5

Philips Semiconductors

Product specification

DVB-C channel receiver

TDA10021HT

SCLT

20

OD

SCLT can be configured to be a control line output or to output the SCL input. This

is controlled by parameter BYPIIC and CTRL_SCLT of register TEST (index 0F).

SCLT is an open-drain output and therefore requires an external pull-up resistor.

ENSERI

21

I

when HIGH this pin enables the serial output transport stream through the

boundary scan pins TRST, TDO, TCK, TDI and TMS (serial interface). Must be set

LOW in bist and boundary scan mode.

TCK

22

I/O

test clock: an independent clock used to drive the TAP controller in boundary scan

mode. In normal mode of operation, TCK must be set LOW. In serial stream mode,

TCK is the clock output (OCLK).

TDI

23

I/O

test data input: the serial input for test data and instruction in boundary scan mode.

In normal mode of operation, TDI must be set LOW. In serial stream mode, the TDI

is the PSYNC output.

24

S

digital supply voltage for the core (1.8 V typ.)

25

G

digital ground for the core

TRST

26

I/O

test reset: this active LOW input signal is used to reset the TAP controller in

boundary scan mode. In normal mode of operation, TRST must be set LOW. In

serial stream mode, TRST is the uncorrectable output (UNCOR).

TMS

27

I/O

test mode select: this input signal provides the logic levels needed to change the

TAP controller from state to state. In normal mode of operation, TMS must be set to

HIGH. In serial stream mode, TMS is the DEN output.

TDO

28

O

test data output: this is the serial test output pin used in boundary scan mode.

Serial data is provided on the falling edge of TCK. In serial stream mode, TDO is

the data output (DO).

GPIO

29

OD

• A Front-End Lock indicator (FEL) (default mode)

interface

GPIO is an open-drain output and therefore requires an external pull-up resistor.

30

S

digital supply voltage for the pads (3.3 V typ.)

31

G

digital ground for the pads

CTRL

32

OD

output and therefore requires an external pull-up resistor.

UNCOR

33

O

uncorrectable packet: this output signal is HIGH when the provided packet is

uncorrectable (during the 188 bytes of the packet). The uncorrectable packet is not

affected by the Reed Solomon decoder, but the MSB of the byte following the sync

byte is forced to logic 1 for the MPEG-2 process: error flag indicator (if RSI and IEI

PSYNC

34

O

pulse synchro: this output signal goes HIGH when the sync byte (0x47) is provided,

then it goes LOW until the next sync byte

OCLK

35

O

output clock: this is the output clock for the DO[7:0] data outputs. OCLK is internally

generated depending on which interface is selected.

DEN

36

O

data enable: this output signal is HIGH when there is valid data on the output bus

DO[7:0]

SYMBOL

PIN

DESCRIPTION