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LTC1408

1408fa

APPLICATIO S I FOR ATIO

1408 F06

3-WIRE SERIAL

INTERFACE LINK

OVDD

CONV

SCK

LTC1408

SDO

VCC

BFSR

BCLKR

TMS320C54x

BDR

OGND

DGND

CONV

0V TO 3V LOGIC SWING

CLK

B13

B12

Figure 7. DSP Serial Interface to TMS320C54x

BOARD LAYOUT AND BYPASSING

Wire wrap boards are not recommended for high resolu-

tion and/or high speed A/D converters. To obtain the best

performance from the LTC1408, a printed circuit board

with ground plane is required. Layout for the printed circuit

board should ensure that digital and analog signal lines are

separated as much as possible. In particular, care should

be taken not to run any digital track alongside an analog

signal track. If optimum phase match between the inputs

is desired, the length of the twelve input wires of the six

input channels should be kept matched. But each pair of

input wires to the six input channels should be kept

separated by a ground trace to avoid high frequency

crosstalk between channels.

High quality tantalum and ceramic bypass capacitors should

be used at the VCC, VDD and VREF pins as shown in the Block

Diagram on the first page of this data sheet. For optimum

performance, a 10

µF surface mount tantalum capacitor

with a 0.1

µF ceramic is recommended for the VCC,VDD and

VREF pins. Alternatively, 10µF ceramic chip capacitors such

as X5R or X7R may be used. The capacitors must be lo-

cated as close to the pins as possible. The traces connect-

ing the pins and the bypass capacitors must be kept short

and should be made as wide as possible. The VCC and VDD

bypass capacitor returns to the ground plane and the VREF

bypass capacitor returns to the Pin 22. Care should be

taken to place the 0.1

µF VCC and VDD bypass capacitor as

close to Pins 24 and 25 as possible.

Figure 6. Recommended Layout

Figure 6 shows the recommended system ground connec-

tions. All analog circuitry grounds should be terminated at

the LTC1408 Exposed Pad. The ground return from the

LTC1408 to the power supply should be low impedance for

noise-free operation. The Exposed Pad of the 32-pin QFN

package is also internally tied to the ground pads. The

Exposed Pad should be soldered on the PC board to reduce

ground connection inductance. All ground pins (GND,

DGND, OGND) must be connected directly to the same

ground plane under the LTC1408.

VDD BYPASS,

0.1

µF, 0402

OVDD BYPASS,

0.1

µF, 0402

VREF BYPASS,

µF, 0805

VCC BYPASS,

0.1

µF, 0402 AND

µF, 0805

HARDWARE INTERFACE TO TMS320C54x

The LTC1408 is a serial output ADC whose interface has

been designed for high speed buffered serial ports in fast

digital signal processors (DSPs). Figure 7 shows an

example of this interface using a TMS320C54X.

The buffered serial port in the TMS320C54x has direct

access to a 2kB segment of memory. The ADC’s serial data

can be collected in two alternating 1kB segments, in real

time, at the full 600ksps conversion rate of the LTC1408.

The DSP assembly code sets frame sync mode at the BFSR

pin to accept an external positive going pulse and the serial

clock at the BCLKR pin to accept an external positive edge

clock. Buffers near the LTC1408 may be added to drive

long tracks to the DSP to prevent corruption of the signal

to LTC1408. This configuration is adequate to traverse a

typical system board, but source resistors at the buffer

outputs and termination resistors at the DSP, may be

needed to match the characteristic impedance of very long

transmission lines. If you need to terminate the SDO

transmission line, buffer it first with one or two 74ACxx

gates. The TTL threshold inputs of the DSP port respond

properly to the 3V swing used with the LTC1408.

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