Data Sheet

AD5673R/AD5677R

Rev. 0 | Page 27 of 31

POWER-DOWN OPERATION

Command 0100 is designated for the power-down function (see

Table 9). These power-down modes are software programmable

by setting 16 bits, Bit DB15 to Bit DB0, in the input shift register.

Two bits are associated with each DAC channel (PD0 and PD1).

Table 12 shows how the state of the two bits corresponds to the

mode of operation of the device.

Any or all DACs (DAC 0 to DAC 15) power down to the selected

mode by setting the corresponding bits. See Table 13 and

Table 14 for the contents of the input shift register during the

power-down/power-up operation.

Table 12. Modes of Operation

PD1

PD0

Operating Mode

0

0

Normal operation

0

1

Power-down mode: 1 kΩ to GND

When both Bit PD1 and Bit PD0 in the input shift register are set

to 0, the device works normally with its normal power consump-

tion of typically 2.3 mA at 5 V. However, for the 1 kΩ to GND

power-down mode, the supply current decreases to typically

2 µA. In addition to this decrease, the output stage switches

internally from the amplifier output to a resistor network of

known value. Therefore, the DAC channel output impedance is

defined when the channel is powered down by internally

connecting the output to GND through a 1 kΩ resistor. The

output stage is shown in Figure 61.

RESISTOR

NETWORK

VOUT

DAC

POWER-DOWN

CIRCUITRY

AMPLIFIER

Figure 61. Output Stage During Power-Down

The bias generator, output amplifier, resistor string, and other

associated linear circuitry are shut down when power-down

mode is activated. However, the contents of the DAC registers

are unaffected in power-down mode, and the DAC registers can

be updated while the device is in power-down mode. The time

required to exit power-down is typically 3 µs for VDD = 5 V.

To reduce the current consumption further, power off the on-chip

reference. See the Internal Reference Setup section.

LOAD DAC (HARDWARE LDAC PIN)

The AD5673R/AD5677R DACs have double buffered interfaces

consisting of two banks of registers: input registers and DAC

registers. The user can write to any combination of the input

registers. Updates to the DAC registers are controlled by

the LDAC pin.

Instantaneous DAC Updating (LDAC Held Low)

For instantaneous updating of the DACs, LDAC is held low while

data is clocked into the input register using Command 0001. Both

the addressed input register and the DAC register are updated on

the 24th clock, and the output changes immediately.

Deferred DAC Updating (LDAC is Pulsed Low)

For deferred updating of the DACs, LDAC is held high while data

is clocked into the input register using Command 0001. All DAC

outputs are asynchronously updated by pulling LDAC low after the

24th clock. The update occurs on the falling edge of LDAC.

SCL

DAC

REGISTER

INTERFACE

LOGIC

AMPLIFIER

LDAC

INPUT

REGISTER

SDA

12-BIT/16-BIT

DAC

VOUTx

VREF

Figure 62. Simplified Diagram of Input Loading Circuitry for a Single DAC

Table 13. 24-Bit Input Shift Register Contents of Power-Down/Power-Up Operation for DAC 7 to DAC 0 Output Channels

[DB23:DB20]

DB19

[DB18:DB16]

DAC 7

DAC 6

DAC 5

DAC 4

DAC 3

DAC 2

DAC 1

DAC 0

[DB15: B14]

[DB13: B12]

[DB11: B10]

[DB9:DB8]

[DB7:DB6]

[DB5:DB4]

[DB3:DB2]

[DB1:DB0]

0100

0

XXX1

[PD1:PD0]

[PD1:PD0]

[PD1:PD0]

[PD1:PD0]

[PD1:PD0]

[PD1:PD0]

[PD1:PD0]

[PD1:PD0]

1

X means don’t care.

Table 14. 24-Bit Input Shift Register Contents of Power-Down/Power-Up Operation for DAC 15 to DAC 8 Output Channels

[DB23:DB20]

DB19

[DB18:DB16]

DAC 15

DAC 14

DAC 13

DAC 12

DAC 11

DAC 10

DAC 9

DAC 8

[DB15: B14]

[DB13: B12]

[DB11: B10]

[DB9:DB8]

[DB7:DB6]

[DB5:DB4]

[DB3:DB2]

[DB1:DB0]

0100

1

XXX1

[PD1:PD0]

[PD1:PD0]

[PD1:PD0]

[PD1:PD0]

[PD1:PD0]

[PD1:PD0]

[PD1:PD0]

[PD1:PD0]

1

X means don’t care.