AD5673R/AD5677R

Data Sheet

Rev. 0 | Page 28 of 31

LDAC MASK REGISTER

Command 0101 is reserved for the hardware LDAC function.

The address bits are ignored. Writing to the DAC using

Command 0101 loads the 16-bit LDAC register (DB15 to DB0).

The default for each channel is 0, that is, the LDAC pin works

normally. Setting DB15 to DB0 to 1 forces this DAC channel to

ignore transitions on the LDAC pin, regardless of the state of the

hardware LDAC pin. This flexibility is useful in applications

where the user wants to select which channels respond to

the LDAC pin.

The LDAC register gives the user extra flexibility and control

over the hardware LDAC pin (see Table 17). Setting the LDAC

bits (DB0 to DB15) to 0 for a DAC channel means that this

channel update is controlled by the hardware LDAC pin.

HARDWARE RESET (RESET)

The RESET pin is an active low reset that allows the outputs to

be cleared to either zero scale or midscale. The clear code value

depends on the model in use and refers to the power-up voltage.

It is necessary to keep the RESET pin low for a minimum time

(see Table 5) to complete the operation. When the RESET signal

is returned high, the output remains at the cleared value until a

new value is programmed. While the RESET pin is low, the outputs

cannot be updated with a new value. Any events on LDAC

or RESET during power-on reset are ignored. If the RESET pin

is pulled low at power-up, the device does not initialize correctly

until the pin is released.

POWER-ON RESET INTERNAL CIRCUIT

The AD5673R/AD5677R contain a power-on reset circuit that

controls the output voltage during power-up. Depending on the

model selected, the output powers up to zero scale (AD5673R-1,

AD5677R-1) or the output powers up to midscale (AD5673R-2,

AD5677R-2). The output remains powered up at this level until

a valid write sequence is made to the DAC.

SOFTWARE RESET

A software executable reset function is also available, which

resets the DAC to the power-on reset code. Command 0110 is

designated for this software reset function. The DAC address

bits must be set to 0x0 and the data bits set to 0x1234 for the

software reset command to execute.

INTERNAL REFERENCE SETUP

The on-chip reference is on at power-up by default. To reduce

the supply current, turn off this reference by setting the software

programmable bit, DB0, in the internal reference setup register.

Table 15 shows how the state of the bit corresponds to the mode

of operation. Command 0111 is reserved for setting up the

internal reference (see Table 9 and Table 18).

Table 15. Internal Reference Setup Register

Bit

Description

DB2

Reserved

DB1

Reserved; set to 0

DB0

Reference enable

DB0 = 0; internal reference enabled (default)

DB0 = 1; internal reference disabled

Table 16. LDAC Overwrite Definition

Load LDAC Register

LDAC Bits (DB15 to DB0)

LDAC Pin

LDAC Operation

0000000000000000

1 or 0

Determined by the LDAC pin.

1111111111111111

X (don’t care)

DAC channels update and override the LDAC pin. DAC channels see LDAC as 1.

Table 17. Write Commands and LDAC Pin Truth Table1

Command

Description

Hardware LDAC Pin State

Input Register Contents

DAC Register Contents

0001

Write to Input Register x

(dependent on LDAC)

VLOGIC

Data update

No change (no update)

GND2

Data update

Data update

0010

Update DAC Register x with

contents of Input Register x

VLOGIC

No change

Updated with input register contents

GND

No change

Updated with input register contents

0011

Write to and update DAC

Channel x

VLOGIC

Data update

Data update

GND

Data update

Data update

1

A high to low hardware LDAC pin transition always updates the contents of the contents of the DAC register with the contents of the input register on channels that

are not masked (blocked) by the LDAC mask register.

2

When LDAC is permanently tied low, the LDAC mask bits are ignored.

Table 18. 24-Bit Input Shift Register Contents for Internal Reference Setup Command1

DB23 (MSB)

DB22

DB21

DB20

DB19

DB18

DB17

DB16

DB1 to DB3

DB2

DB1

DB0 (LSB)

0

1

1

1

X

X

X

X

X

0

0

1/0

Command bits (C3 to C0)

Address bits (A3 to A0)

Don’t care

Reserved

Reserved

Reference setup register

1

X means don’t care.