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Data Sheet

AD5673R/AD5677R

Rev. 0 | Page 23 of 31

THEORY OF OPERATION

DIGITAL-TO-ANALOG CONVERTER (DAC)

The AD5673R/AD5677R are 16-channel, 12-/16-bit, serial input,

voltage output DACs with an internal reference. The devices

operate from supply voltages of 2.7 V to 5.5 V. Data is written to the

AD5673R/AD5677R in a 24-bit word format via a 2-wire serial

interface. The AD5673R/AD5677R incorporate a power-on

reset circuit to ensure that the DAC output powers up to a

known output state. The devices also have a software power-

down mode that reduces the typical current consumption to 2 µA.

TRANSFER FUNCTION

The internal reference is on by default.

The gain of the output amplifier can be set to ×1 or ×2 using the

span set pin (GAIN). When the GAIN pin is tied to GND, all

16 DAC outputs have a span from 0 V to VREF. When the GAIN pin

is tied to VLOGIC, all 16 DACs output a span of 0 V to 2 × VREF.

DAC ARCHITECTURE

The AD5673R/AD5677R implement a segmented string DAC

architecture with an internal output buffer. Figure 55 shows the

internal block diagram.

INPUT

2.5V

REF

DAC

RESISTOR

STRING

REF (+)

REF (–)

VREF

VOUTx

GND

GAIN

(GAIN = 1 OR 2)

Figure 55. Single DAC Channel Architecture Block Diagram

The resistor string structure is shown in Figure 56.

TO OUTPUT

AMPLIFIER

VREF

Figure 56. Resistor String Structure

The code loaded to the DAC register determines the node on

the string where the voltage is tapped off and fed into the output

amplifier. The voltage is tapped off by closing one of the

switches and connecting the string to the amplifier. Because

each resistance in the string has the same value, R, the string

DAC is guaranteed monotonic.

Internal Reference

The AD5673R/AD5677R on-chip reference is enabled at power-up,

but the on-chip reference can be disabled via a write to the

control register. See the Internal Reference Setup section for

details.

The AD5673R/AD5677R have a 2.5 V, 2 ppm/°C reference, giving

a full-scale output of 2.5 V or 5 V, depending on the state of the

GAIN pin. The internal reference associated with the device is

available at the VREF pin. This buffered reference is capable of

driving external loads of up to 15 mA.

Output Amplifiers

The output buffer amplifier generates rail-to-rail voltages on its

output, which gives an output range of 0 V to VDD. The actual

range depends on the value of the voltage reference level (VREF)

the GAIN pin, the offset error, and the gain error.

The output amplifiers can drive a load of 1 kΩ in parallel with

10 nF to GND. The slew rate is 0.8 V/µs with a typical ¼ to ¾

scale settling time of 6 µs.

SERIAL INTERFACE

The AD5673R/AD5677R use a 2-wire, I2C-compatible serial

interface. These devices can be connected to an I2C bus as a

slave device under the control of the master devices. The

AD5673R/AD5677R support standard (100 kHz) and fast

(400 kHz) data transfer modes. Support is not provided for

10-bit addressing and general call addressing.

Input Shift Register

The input shift register of the AD5673R/AD5677R is 24 bits wide.

Data is loaded MSB first (DB23), and the first four bits are the

command bits, C3 to C0 (see Table 9), followed by the 4-bit

DAC address bits, A3 to A0 (see Table 10), and finally, the

16-bit data-word.

The data-word comprises a 16-bit input code for the AD5677R,

and a 12-bit input code followed by four zeros, or don’t care

bits, for the AD5673R (see Figure 57 and Figure 58). These data

bits are transferred to the input register on the 24 falling edges

of SCL.

Commands execute on individual DAC channels, combined DAC

channels, or on all DACs, depending on the address bits selected.

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