AD8065 datasheet(49/59 Pages) AD

49 / 59 page

Data Sheet

AD3551R

REGISTERS

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Rev. A | 49 of 59

Table 37. Bit Descriptions for ERR_ALARM_MASK (Continued)

Bits

Bit Name

Settings

Description

Reset

Access

REF_RANGE_ALARM_MASK

Reference Alarm Mask. When set, the

user can ignore alarms due to the

reference dipping below 2 V.

0x0

R/W

CLOCK_COUNT_ERR_ALARM_MASK

Clock Count Error Alarm Mask. When

set, the user can ignore alarms due to

an insufficient number of clock periods

for a user write.

0x0

R/W

MEM_CRC_ERR_ALARM_MASK

Memory CRC Error Alarm Mask. When

set, the user can ignore alarms due to a

memory CRC error.

0x0

R/W

SPI_CRC_ERR_ALARM_MASK

SPI CRC Error Alarm Mask. When set,

the user can ignore alarms due to the

SPI CRC checker.

0x0

R/W

WRITE_TO_READ_ONLY_ALARM_MASK

Write to Read-Only Alarm Mask. When

set, the user can ignore alarms due to

the user writing to a read-only register.

0x0

R/W

PARTIAL_REGISTER_ACCESS_ALARM_MASK

Partial Register Access Alarm Mask.

When set, the user can ignore alarms

due to the user not completing the write

to a register.

0x0

R/W

REGISTER_ADDRESS_INVALID_ALARM_MASK

When set, the user can ignore alarms

due to the user writing to an invalid

0x0

R/W

Error Status Register

Address: 0x17, Reset: 0x01, Name: ERR_STATUS

This register signals a combination of errors in the analog and digital domains. All the bits are sticky and can be cleared by writing 1.

Table 38. Bit Descriptions for ERR_STATUS

Bits

Bit Name

Settings

Description

Reset

Access

RESERVED

Reserved.

0x0

REF_RANGE_ERR_STATUS

Reference Alarm Error Status.

This bit indicates an alarm if the

reference dips below 2 V.

0x0

R/W1C

DUAL_SPI_STREAM_EXCEEDS_DAC_ERR_STATUS

Dual SPI Exceeds DAC Memory

Map During Streaming. This bit

indicates an alarm when in dual SPI

and streaming access goes beyond

the DAC memory map.

0x0

R/W1C

MEM_CRC_ERR_STATUS

Memory Map Background CRC

Error. This bit indicates an alarm

when the background CRC detects

0x0

R/W1C

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