Data Sheet

AD3551R

TABLE OF CONTENTS

analog.com

Rev. A | 2 of 59

Features................................................................ 1

Applications........................................................... 1

General Description...............................................1

Functional Block Diagram......................................1

Specifications........................................................ 4

Electrical Characteristics.................................... 4

AC Characteristics..............................................5

Timing Characteristics........................................6

Absolute Maximum Ratings.................................10

Thermal Resistance......................................... 10

ESD Caution.....................................................10

Pin Configuration and Function Descriptions.......11

Typical Performance Characteristics................... 12

Terminology......................................................... 21

Theory of Operation.............................................22

Product Description.......................................... 22

DAC Architecture..............................................22

Predefined Output Voltage Spans....................22

Custom Output Voltage Span...........................23

Transfer Function............................................. 23

VREF..................................................................23

SPI Register Map Access.................................23

Serial Interface................................................. 30

DAC Update Modes......................................... 32

Power-Down.....................................................33

Reset................................................................33

Error Detection................................................. 33

ALERT Pin........................................................34

Device ID..........................................................35

Summary of Interface Access Modes...............35

Registers............................................................. 36

Register Summary............................................36

Interface Register Details................................. 39

DAC Register Details....................................... 48

Applications Information...................................... 57

Power Supply Recommendations.................... 57

Layout Guidelines.............................................57

Outline Dimensions............................................. 59

Ordering Guide.................................................59

Evaluation Boards............................................ 59

REVISION HISTORY

3/2023—Rev. 0 to Rev. A

Changed 16-Bit, 33 MUPS, Multispan, Multi-IO SPI DAC to Single Channel, 16-Bit, 33 MUPS,

Multispan, Multi-IO SPI DAC..........................................................................................................................1

Changed DVDD to DVDD, IOVDD to VLOGIC, VREF to VREF, AVDD to AVDD, VDD to AVDD (Throughout)......1

Changes to General Description Section and Table 1..................................................................................... 1

Changes to Table 2..........................................................................................................................................4

Changes to Table 3..........................................................................................................................................5

Changes to Table 5........................................................................................................................................10

Changes to Figure 12 and Table 7................................................................................................................. 11

Deleted Figure 51; Renumbered Sequentially............................................................................................... 18

Added Figure 65 and Figure 66; Renumbered Sequentially..........................................................................20

Changes to Relative Accuracy or Integral Nonlinearity (INL) Section............................................................21

Changes to Differential Nonlinearity (DNL) Section.......................................................................................21

Change to DC PSRR and AC PSRR Section................................................................................................ 21

Changes to Output Voltage Settling Time Section.........................................................................................21

Changes to Digital-to-Analog Glitch Impulse Section.................................................................................... 21

Changes to Digital Feedthrough Section....................................................................................................... 21

Changes to Output Noise Spectral Density Section...................................................................................... 21

Changes to Total Harmonic Distortion (THD) Section....................................................................................21

Changes to Product Description Section....................................................................................................... 22

Changes to DAC Architecture and Figure 67.................................................................................................22

Changes to Predefined Output Voltage Spans and Table 8...........................................................................22

Changes to Custom Output Voltage Span Section ....................................................................................... 23

Added Table 9 and Table 10; Renumbered Sequentially .............................................................................. 23

Changes to Transfer Function Section ..........................................................................................................23

Change to SPI Frame Synchronization Section ............................................................................................23