AD8065 datasheet(23/59 Pages) AD

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Data Sheet

AD3551R

THEORY OF OPERATION

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Rev. A | 23 of 59

CUSTOM OUTPUT VOLTAGE SPAN

In addition to the predefined output span ranges configured

via the CH0_OUTPUT_RANGE register, the output span range

can be customized by programming the offset and gain reg-

isters in conjunction with the external feedback resistor. The

CHx_RANGE_OVERRIDE bit must be set in the CHx_GAIN reg-

ister to override the predefined range and offset values. Gain is

configured as a combination of two parameters, CHx_GAIN_SCAL-

ING_P and CHx_GAIN_SCALING_N, in the CHx_GAIN register.

The absolute value and the sign of the offset are configured in the

CHx_OFFSET register and the lower bits of the CHx_GAIN register,

as shown in Table 10.

The zero-scale output voltage (VOUT_ZS) and full-scale output volt-

age (VOUT_FS) are calculated using the following equations:

VOUT_ZS=2.5+1.6×RFB× Offset−GainP

VOUT_FS=2.5+1.6×RFB× Offset+GainN

where:

GainP= 1

2CHx_GAIN_SCALING_P

GainN= 1

2CHx_GAIN_SCALING_N

Offset=OFFSET_POLARITY × CHx_OFFSET

1024

OFFSET_POLARITY = 1 if CHx_OFFSET_POLARITY = 0 and −1

if CHx_OFFSET_POLARITY = 1, and the value of RFB depends on

which RFBx_y pin is connected, as shown in Table 9.

Table 9. Value of Resistors on RFBx_y pins

Resistor Value (kΩ)

RFB1_y

1.610938

RFB2_y

3.228125

RFB4_y

6.488125

Table 10. Mapping of Offset Value

Item

Bit

Field Name

Offset Sign

CHx_GAIN

CHx_OFFSET_POLARITY

Offset Bit 8

CHx_GAIN

CHx_OFFSET[8]

Offset Bit 7 to Bit 0

CHx_OFFSET

[7:0]

CHx_OFFSET

At zero offset, a custom range is centered at VCM (2.5 V). The offset

That is, a 10 V range spans from −2.5 V to 7.5 V at zero offset, and

can be shifted by ±2.5 V using the offset register and polarity bit.

The gain scaling configuration does not affect the amplitude of the

offset.

While several combinations of RFB and gain scaling values are

possible to define a given range, it is recommended to use the

lowest possible value of RFB to minimize the noise density at the

output of the TIA.

TRANSFER FUNCTION

The conversion of the digital code to the DAC output current follows

a linear relation with the code in plain binary. The ideal output

current, in mA, is given by the following equation:

IOUTx=1.6× GainP−Offset− D216× GainP+GainN

where:

D is the decimal equivalent of the binary code that is loaded in the

DAC register.

Offset, GainP, and GainN are according to the definitions given in

the Custom Output Voltage Span section.

The conversion of current to voltage is performed in the external

TIA. If the internal feedback resistor is used, the output voltage

follows the following equation:

VOUT=VCM−RFB×IOUT

where:

VCM is the common-mode voltage at the VCMx pin that is connected

to the noninverting input of the TIA, nominally 2.5 V.

RFB is according to the definition given in Table 9.

VREF

The AD3551R has an internal 2.5 V voltage reference with a

3 ppm/°C temperature coefficient that is enabled at power-up. The

VREF pin is in high impedance at power-up to avoid electrical

problems. If the internal reference must be used externally, the

REFERENCE_VOLTAGE_SEL bits in the REFERENCE_CONFIG

Table 11.

When the external reference is selected, the VREF pin behaves as

an input.

Table 11. Voltage Reference Selection

REFERENCE_VOLTAGE_SEL

Source

VREF I/O

Internal

Floating

Internal

2.5 V

External

Input

External

Input

SPI REGISTER MAP ACCESS

SPI Frame Synchronization

The CS signal frames data during an SPI transaction. A falling edge

on CS enables the digital interface and initiates an SPI transaction.

Each SPI transaction consists of at least one instruction phase and

data phase, as described in the Instruction Phase section and the

Data Phase section. For all SPI transactions, data is aligned MSB

first. Deasserting CS during an SPI transaction terminates part or

all of the data transfer and disables the digital interface. If CS is

deasserted (returned high) after one or more register addresses

are issued, those registers are written or read, but any partially

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