AD5116 datasheet(19/28 Pages) AD

19 / 28 page

Data Sheet

AD5110/AD5112/AD5114

THEORY OF OPERATION

analog.com

Rev. D | 19 of 28

The AD5110/AD5112/AD5114 digital programmable resistors are

designed to operate as true variable resistors for analog signals

within the terminal voltage range of GND < VTERM < VDD. The resis-

tor wiper position is determined by the RDAC register contents. The

RDAC register acts as a scratchpad register that allows unlimited

changes of resistance settings.

The RDAC register can be programmed with any position setting

using the I2C interface. Once a desirable wiper position is found,

this value can be stored in the EEPROM memory. Thereafter, the

wiper position is always restored to that position for subsequent

power-up. The storing of EEPROM data takes approximately 18

ms; during this time, the device is locked and does not acknowl-

edge any new command, thus preventing any changes from taking

place.

RDAC REGISTER AND EEPROM

The RDAC register directly controls the position of the digital poten-

tiometer wiper. For example, when the RDAC register is loaded with

0x3F (128-taps), the wiper is connected to full scale of the variable

resistor. The RDAC register is a standard logic register; there is no

restriction on the number of changes allowed.

It is possible to both write to and read from the RDAC register using

the I2C interface (see Table 10).

The contents of the RDAC register can be stored to the EEPROM

using Command 1 (Table 10). Thereafter, the RDAC register is

always set at that position for any future on-off-on power supply

sequence. It is possible to read back the data saved into the

EEPROM with Command 6 in Table 10. In addition, the resistor

tolerance error is saved within the EEPROM; this can be read

back and used to calculate the end-to-end tolerance, providing an

accuracy of 0.1%.

Low Wiper Resistance Feature

The AD5110/AD5112/AD5114 include extra steps to achieve a mini-

mum resistance between Terminal W and Terminal A or Terminal B.

These extra steps are called bottom scale and top scale. At bottom

scale, the typical wiper resistance decreases from 70 Ω to 45 Ω.

At top scale, the resistance between Terminal A and Terminal W is

decreased by 1 LSB, and the total resistance is reduced to 70 Ω.

The extra steps are not equal to 1 LSB and are not included in the

INL, DNL, R-INL, and R‑DNL specifications.

I2C SERIAL DATA INTERFACE

The AD5110/AD5112/AD5114 have 2-wire I2C-compatible serial

interfaces. These devices can be connected to an I2C bus as a

target device under the control of a controller device. See Figure 3

for a timing diagram of a typical write sequence.

The AD5110/AD5112/AD5114 support standard (100 kHz) and fast

(400 kHz) data transfer modes. Support is not provided for 10-bit

addressing and general call addressing.

The 2-wire serial bus protocol operates as follows:

1. The controller initiates data transfer by establishing a start

condition, which is when a high-to-low transition on the SDA

line occurs while SCL is high. The following byte is the address

byte, which consists of the 7-bit target address and an R/W

bit. The target device corresponding to the transmitted address

responds by pulling SDA low during the ninth clock pulse (this is

termed the acknowledge bit). At this stage, all other devices on

the bus remain idle while the selected device waits for data to

be written to, or read from, its shift register.

2. If the R/W bit is set high, the controller reads from the target

device. However, if the R/W bit is set low, the controller writes to

the target device.

3. Data is transmitted over the serial bus in sequences of nine

clock pulses (eight data bits followed by an acknowledge bit).

The transitions on the SDA line must occur during the low

period of SCL and remain stable during the high period of SCL.

4. When all data bits have been read or written, a stop condition

is established. In write mode, the controller pulls the SDA line

high during the 10th clock pulse to establish a stop condition. In

read mode, the controller issues a no acknowledge for the ninth

clock pulse (that is, the SDA line remains high). The controller

brings the SDA line low before the 10th clock pulse, and high

during the 10th clock pulse to establish a stop condition.

I2C Address

The AD5110/AD5112/AD5114 each have two different target ad-

dress options available. See Table 9 for a list of target addresses.

Table 9. Device Address Selection

Model

7-Bit I2C Device Address

AD511X1 BCPZ Y2

0101111

AD511X1 BCPZ Y2- 1

0101100

1 Model.

2 Resistance.

INPUT SHIFT REGISTER

For the AD5110/AD5112/AD5114, the input shift register is 16 bits

wide (see Figure 2). The 16-bit word consists of five unused bits

(should be set to zero), followed by three control bits, and eight

RDAC data bits. If the RDAC register is read from or written to

in the AD5112, Bit DB0 is a don’t care. The RDAC register is

read from or written to in the AD5114, Bit DB0 and DB1 are don’t

cares. Data is loaded MSB first (Bit DB15). The three control bits

determine the function of the software command (Table 10). Figure

3 shows a timing diagram of a typical AD5110/AD5112/AD5114

write sequence.

The command bits (Cx) control the operation of the digital potenti-

ometer and the internal EEPROM. The data bits (Dx) are the values

that are loaded into the decoded register.

AD5116 Datasheet(PDF) 19 Page - Analog Devices

AD5116 Datasheet(HTML) 19 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

Datasheet Download

Link URL