ADN2913

Data Sheet

Rev. B | Page 32 of 35

Choosing AC Coupling Capacitors

AC coupling capacitors at the inputs (PIN, NIN) and outputs

(DATOUTP, DATOUTN) of the ADN2913 must be chosen

such that the device works properly over the full range of data

rates used in the application. When choosing the capacitors, the

time constant formed with the two 50 Ω resistors in the signal

path must be considered. When a large number of consecutive

identical digits (CIDs) are applied, the capacitor voltage can

droop due to baseline wander (see Figure 32), causing pattern

dependent jitter (PDJ).

The user must determine how much droop is acceptable and

choose an ac coupling capacitor based on that amount of droop.

The amount of PDJ can then be approximated based on the

capacitor selection. The actual capacitor value selection may

require some trade-offs between droop and PDJ.

For example, assuming that 2% droop is acceptable, the

maximum differential droop is 4%.

Normalizing to V p-p,

Droop = Δ V = 0.04 V = 0.5 V p-p (1 − e−t/τ)

Therefore,

τ = 12t

where:

τ is the RC time constant (C is the ac coupling capacitor, R = 100 Ω

seen by C).

t is the total discharge time.

t = nΤ

where:

n is the number of CIDs.

T is the bit period.

Calculate the capacitor value by combining the equations for τ

and t.

C = 12nT/R

When the capacitor value is selected, the PDJ can be

approximated as

PDJps p-p = 0.5tR(1 − e(−nT/RC)/0.6

where:

PDJps p-p is the amount of pattern dependent jitter allowed,

<0.01 UI p-p typical.

tR is the rise time, which is equal to 0.22/BW; BW ≈ 0.7 (bit rate).

Note that this expression for tR is accurate only for the inputs.

The output rise time for the ADN2913 is ~30 ps regardless of

data rate.

NOTES

1. DURING THE DATA PATTERNS WITH HIGH TRANSITION DENSITY, THE DIFFERENTIAL DC VOLTAGE AT V1 AND V2 IS ZERO.

2. WHEN THE TIA OUTPUTS CONSECUTIVE IDENTICAL DIGITS, V1 AND V1b ARE DRIVEN TO DIFFERENT DC LEVELS. V2 AND V2b DISCHARGE TO

THE VREF LEVEL, WHICH EFFECTIVELY INTRODUCES A DIFFERENTIAL DC OFFSET ACROSS THE AC COUPLING CAPACITORS.

3. WHEN THE BURST OF DATA STARTS AGAIN, THE DIFFERENTIAL DC OFFSET ACROSS THE AC COUPLING CAPACITORS IS APPLIED TO THE

INPUT LEVELS, CAUSING A DC SHIFT IN THE DIFFERENTIAL INPUT. THIS SHIFT IS LARGE ENOUGH SUCH THAT ONE OF THE STATES, EITHER

HIGH OR LOW, DEPENDING ON THE LEVELS OF V1 AND V1b WHEN THE TIA BEGAN DETECTING AND OUTPUTTING A CID DATA SYSTEM, IS CANCELLED OUT.

THE QUANTIZER DOES NOT RECOGNIZE THIS AS A VALID STATE.

4. THE DC OFFSET SLOWLY DISCHARGES UNTIL THE DIFFERENTIAL INPUT VOLTAGE EXCEEDS THE SENSITIVITY OF THE ADN2913. THE

QUANTIZER RECOGNIZES BOTH HIGH AND LOW STATES AT THIS POINT.

V1

V1b

V2

V2b

VDIFF

VDIFF = V2 – V2b

VTH = ADN2913 QUANTIZER THRESHOLD

2

34

1

VREF

VTH

CDR

VREF

50Ω

50Ω

PIN

NIN

ADN2913

COUT

DATOUTP

DATOUTN

CIN

V2

V2b

V1

V1b

TIA

VCC

2

Figure 32. Example of Baseline Wander