ADN2913 datasheet(20/35 Pages) AD

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ADN2913

Data Sheet

Rev. B | Page 20 of 35

THEORY OF OPERATION

The ADN2913 implements clock and data recovery for data

rates between 6.5 Mbps and 8.5 Gbps. A front end is configurable

to either amplify or equalize the nonreturn-to-zero (NRZ) input

waveform to full-scale digital logic levels, or to bypass a full

digital logic signal.

The user can choose one of three input stages to process the

data: a high gain limiting amplifier with better than 10 mV

sensitivity, a high-pass passive equalizer with up to 10 dB of

boost at 5 GHz, or a 0 dB EQ buffer with 600 mV sensitivity.

An on-chip LOS detector works with the high sensitivity limiting

amplifier. The default threshold for the LOS detector is the

sensitivity of the device, with a maximum threshold level of

128 mV p-p. The limiting amplifier slice threshold can use a

factory trim setting, a user defined threshold set by the I2C

interface, or an adjusted level for the best eye opening at the

phase detector.

When the input signal is corrupted due to FR-4 or other

impairments in the printed circuit board (PCB) traces, a passive

equalizer can be one of the signal integrity options. The equalizer

high frequency boost is configurable through the I2C registers.

A user enabled adaptation is included that automatically adjusts

the equalizer to achieve the widest eye opening. The equalizer

can be manually set for any data rate, but adaptation is available

only at data rates greater than 5.5 Gbps.

When a signal is presented to the clock and data recovery (CDR)

system, the ADN2913 acts as a delay-locked and phase-locked

loop (PLL) circuit for clock recovery and data retiming from an

NRZ encoded data stream. Input data is sampled by a high speed

clock. A digital downsampler accommodates data rates spanning

three orders of magnitude. Downsampled data is applied to a

binary phase detector (see Figure 23).

The phase of the input data signal is tracked by two separate

feedback loops. A high speed delay-locked loop (DLL) path

combines a digital integrator with a digitally controlled phase

shifter (PSH) on the DCO clock to track the high frequency

components of jitter.

A separate PLL composed of a digital integrator and DCO

tracks the low frequency components of jitter. The initial

frequency of the DCO is set by a third loop that compares the

DCO frequency with the input data frequency. This third loop

also sets the decimation ratio of the digital downsampler.

The delay-locked and PLLs together track the phase of the input

data. For example, when the clock lags the input data, the phase

detector drives the DCO to a higher frequency and decreases the

delay of the clock through the phase shifter; both of these actions

serve to reduce the phase error between the clock and data.

Because the loop filter is an integrator, the static phase error is

driven to zero.

Another view of the circuit is that the phase shifter implements

the zero required for frequency compensation of a second-order

PLL. This zero is placed in the feedback path and, therefore,

does not appear in the closed-loop transfer function. Because

this circuit has no zero in the closed-loop transfer, jitter peaking

is eliminated.

The combination of the delay-locked and PLLs simultaneously

provide wideband jitter tolerance and narrow-band jitter

filtering. The simplified block diagram in Figure 23 shows that

Z(s)/X(s) is a second-order low-pass jitter transfer function that

provides excellent filtering. The low frequency pole is formed by

dividing the gain of the PLL by the gain of the DLL, where the

upsampling and zero-order hold in the DLL has a gain approaching

N at the transfer bandwidth of the loop. Note that the jitter transfer

has no zero, unlike an ordinary second-order PLL. This means that

the main PLL loop has no jitter peaking, making the circuit ideal

for signal regenerator applications, where jitter peaking in a cascade

of regenerators can contribute to hazardous jitter accumulation.

The error transfer, e(s)/X(s), has the same high-pass form as an

ordinary PLL up to the slew rate limit of the DLL with a binary

phase detector. This transfer function can be optimized to give

excellent wideband jitter tolerance because the jitter transfer

function, Z(s)/X(s), provides the narrow-band jitter filtering.

PSH

Z(s)

RECOVERED

CLOCK

KDLL

I – z–1

KDCO

I – z–N

I – z–1

KPLL × TRANBW

I – z–1

DELAY-LOCKED LOOP (DLL)

PHASE-LOCKED LOOP (PLL)

ZERO-ORDER HOLD

SAMPLE CLOCK

INPUT

DATA

÷N

BINARY

PHASE

DETECTOR

X(s)

KPLL × TRANBW – KDCO

s × N × PSH × KDLL + KPLL × TRANBW × KDCO

Z(s)

X(s)

Figure 23. CDR Jitter Block Diagram

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