LTC6907 datasheet(12/28 Pages) AD

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LTC6995-1/LTC6995-2

Rev. B

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Changing DIVCODE After Start-Up

Following start-up, the A/D converter will continue moni-

toring VDIV for changes. The LTC6995 will respond to

DIVCODE changes in less than one cycle.

tDIVCODE < 500 • tMASTER < tOUT

The output may have an inaccurate pulse width during the

frequency transition. But the transition will be glitch-free

and no high or low pulse can be shorter than the mas-

ter clock period. A digital filter is used to guarantee the

DIVCODEhassettledtoanewvaluebeforemakingchanges

to the output.

Start-Up Time

When power is first applied, the power-on reset (POR)

circuit will initiate the start-up time, tSTART. A supply

voltage of typically 1.4V (1.2V to 1.5V over temperature)

initiates the start-up sequence. The OUT pin is held low

during this time. The typical value for tSTART ranges from

0.5msto8msdependingonthemasteroscillatorfrequency

(independent of NDIV):

tSTART(TYP) = 500 • tMASTER

During start-up, the DIV pin A/D converter must deter-

mine the correct DIVCODE before the output is enabled.

The start-up time may increase if the supply or DIV pin

voltages are not stable. For this reason, it is recommended

to minimize the capacitance on the DIV pin so it will prop-

erly track V+. Less than 100pF will not affect performance.

Start-Up Behavior

Whenfirstpoweredup,theoutputisheldlow.Ifthepolarity

is set for non-inversion (POL = 0) and the output is enabled

at the end of the start-up time, OUT will begin oscillating.

If the output is being reset (RST = 1 for LTC6995-1 and

RST = 0 for LTC6995-2) at the end of the start-up time,

it will remain low due to the POL bit = 0. When reset is

released the oscillator starts and the output remains low

for precisely one half cycle of the programmed period.

In inverted operation (POL = 1), the start-up sequence is

similar. However, the LTC6995 does not know the correct

DIVCODE setting when first powered up, so the output

defaults low. At the end of tSTART, the value of DIVCODE is

recognizedandOUTgoeshigh(inactive)becausePOL = 1.

If the output is being reset (RST = 1 for LTC6995-1 and

RST = 0 for LTC6995-2) at the end of the start-up time,

it will remain high due to the POL bit = 1. When reset is

released the oscillator starts and the output remains high

for precisely one half cycle of the programmed period.

Figure7toFigure10detailthepossiblestart-upsequences.

DIV

200mV/DIV

OUT

1V/DIV

10ms/DIV

699512

F05

V+ = 3.3V

RSET = 200k

V+

1V/DIV

OUT

1V/DIV

250µs/DIV

699512 F06

V+ = 2.5V

DIVCODE = 15

RSET = 50k

500µs

Figure 5. DIVCODE Change from 1 to 0

Figure 6. Typical Start-Up LTC6995-1 with RST = 0V

OPERATION

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