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MGR230

8

8

TRANSMIT REGISTER

RECEIVE REGISTER

STATUS REGISTER

SYNCHRONOUS IN REGISTER

SYNCHRONOUS OUT REGISTER

GUARD TIME REGISTER

CONFIGURATION REGISTER

ISO 7816 UART

LOW ADDRESS REGISTER

HIGH ADDRESS REGISTER

MEMORY READ REGISTER

MEMORY WRITE REGISTER

AUXILIARY RAM

PERIPHERAL EXTENSION REGISTER

ON/OFF SEQUENCER

INTERFACE, SECURITY AND POWER CONTROL

CLOCK CONFIGURATION REGISTER

PROGRAMMABLE DIVIDER

CLOCK GENERATOR

MICRO CLOCK

UART

CLOCK

CARD

CLOCK

EXTERNAL

CLOCK

XTAL

I/O

C4

C8

K0

K1 K2 K3 CMDVCC RST DET ERR POR

CLK

CLKOUT OSCINT XTAL1

80C52 CORE

P17

P00/P07

8

P20/P27

ALE

P32/INT0

P15 P14 P13 P12

P40 to P47

P34 P35 P16

OSC

RESET

databus

control bus

PSEN

EA

P37/RD

P36/WR

P33/INT1

P30/RXD P31/TXD

P10/T2 P11/T2EX

Fig.6 Peripheral interface.