TDA8006HSLASHC2 datasheet(14/40 Pages) PHILIPS

14 / 40 page

2000 Feb 21

Philips Semiconductors

Product speciﬁcation

Multiprotocol IC Card coupler

TDA8006

Table 4

X = don’t care.

AD3

AD2

AD1

AD0

R/W

PERIPHERAL

00000

CCR (Clock Conﬁguration Register)

clock generator

00010

PDR (Programmable Divider Register)

00110

SOR (Synchronous Output Register)

ISO 7816 UART

00111

SIR (Synchronous Input Register)

01000

UTR (UART Transmit Register)

01001

URR (UART Receive Register)

01011

USR (UART Status Register)

01010

UCR (UART Conﬁguration Register)

01100

GTR (Guard Time Register)

01110

PER (Ports Extension Register)

on/off sequencer

MAR0 (Memory Address LOW)

auxiliary RAM

MAR1 (Memory Address HIGH)

MWR (Memory Write Register)

MRR (Memory Read Register)

Clock circuit

The microcontroller clock (OSC), the card clock (CLK), the

ISO 7816 UART clock, and the clock to the external world

(CLKOUT), are derived from the main clock signals (XTAL

from 4 to 20 MHz, or an external clock signal applied to

XTAL1), or the internal oscillator (fINT).

• Microcontroller clock (OSC): after power-on or reset, the

microcontroller is clocked at 1

⁄8fINT. Then, the application

may decide to clock it at 1

⁄2fINT, 1⁄2fxtal or fxtal.

All frequency changes are synchronous, thereby

ensuring no hang-up due to short spikes etc.

• Card clock (CLK): the application may send a clock

frequency of 1

⁄2fxtal, 1⁄4fxtal, 1⁄8fxtal or 1⁄2fINT (≈1.25 MHz),

or may stop the clock at HIGH or LOW. All transitions

are synchronous, ensuring correct pulse length during

start or change, in accordance with ISO 7816. After

power-on or reset, CLK is held LOW.

• External clock output (CLKOUT): CLKOUT is a

permanent clock output for external use. The following

frequencies are possible: fxtal, 1⁄2fxtal and 1⁄4fxtal.

All transitions are synchronous. After power-on or reset,

CLKOUT is fixed at 1

⁄4fxtal.

• ISO 7816 UART clock: the clock to the ISO 7816 UART

is identical to the clock to the card (CLK).

To achieve the different I/O baud rates as defined by

values F and D (see Table 7), the clock signal is counted

by an auto-reload 8-bit programmable counter and then

divided by a 31 or 32 prescaler.

All these configurations are controlled by the clock

configuration register and by the programmable divider

TDA8006H/C2 Datasheet(PDF) 14 Page - NXP Semiconductors

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