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TDA8366 Datasheet(PDF) 21 Page - NXP Semiconductors |
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TDA8366 Datasheet(HTML) 21 Page - NXP Semiconductors |
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21 / 48 page  January 1995 21 Philips Semiconductors Objective specification I2C-bus controlled PAL/NTSC TV processor TDA8366 LUMINANCE INPUTS AND OUTPUTS (PINS 25 AND 26) V26(p-p) output signal amplitude (peak-to-peak value) top sync-white − 0.45 0.63 V VTS top sync level − 2.5 − V Zo output impedance − 250 −Ω V25(p-p) input signal amplitude (peak-to-peak value) − 0.45 − V Iclamp clamp current during burst key pulse − 200 −µA Ii input current no clamp −− 0.5 µA Chrominance filters CHROMINANCE TRAP CIRCUIT ftrap trap frequency − fosc − MHz QF trap quality factor note 16 − 2 − SR colour subcarrier rejection 20 −− dB CHROMINANCE BANDPASS CIRCUIT fc centre frequency − fosc − MHz QBP bandpass quality factor − 3 − Delay line and peaking circuit Y DELAY LINE td delay time note 6 − 480 − ns td1 tuning range delay time 8 steps −160 − +160 ns B bandwidth of internal delay line note 6 5 −− MHz PEAKING CONTROL; note 17 fc(p) peaking centre frequency − 3 − MHz tW width of preshoot or overshoot note 2 − 160 − ns OS overshoot positive − 20 − % negative − 36 − % peaking control curve 16 steps see Fig.5 CORING STAGE S coring range − 15 − IRE GW wave gain − 1.8 − Horizontal synchronization circuits SYNC VIDEO INPUT (PINS 9, 11 AND 15) V9,11,15 sync pulse amplitude note 2 50 300 − mV SLHS slicing level for horizontal sync note 18 − 50 − % SLVS slicing level for vertical sync − 30 − % SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT negative half wave gain positive half wave gain -------------------------------------------------------------- |
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