M66239FP

Rev.1.00 Mar 16, 2005 page 20 of 23

Frequency Modulation Characteristics

(Ta = 0 to +50°C, Vcc = 3.15 to 3.46V, GND = 0V)

Item

Symbol

Min

Typ

Max

Unit

Test Conditions

Frequency modulation start position

Tstart

100

256

1023

Cycle

Frequency modulation period

Trate

1500

8192

65535

Cycle

Center frequency

Fcenter

±0

—

±2.55

%

Center frequency resolution

Fstep1

0.01

—

—

%

Peak frequency (+ side)

Fpeak+

+0.3

—

+2.55

%

Peak frequency (– side)

Fpeak–

–0.3

—

–2.55

%

Peak frequency resolution

Fstep2

0.01

—

—

%

1st.pole position

1stPole

Tstart+500

—

40959

Cycle

2nd.pole position

2ndPole

1stPole+500

—

40959

Cycle

3rd.pole position

3rdPole

2ndPole+500

—

40959

Cycle

4th.pole position

4thPole

3rdPole+500

—

40959

Cycle

Min cycle between 1stPole and Tstart

Tspace1

500

—

—

Cycle

Min cycle between 2ndPole and 1stPole

Tspace2

500

—

—

Cycle

Min cycle between 3rdPole and 2ndPole

Tspace3

500

—

—

Cycle

Min cycle between 4thPole and 3rdPole

Tspace4

500

—

—

Cycle

Min cycle between modulation end-4thPole

Tspace5

500

—

—

Cycle

Min cycle between modulation end-2ndPole

(In case of mode 2 or mode 3)

Tspace6

500

—

—

%

1st.Pole frequency (In case of page 12)

Fcenter–0.1

—

–Fpeak+0.1

%

1st.Pole frequency (In case of page 13)

F1stpole

Fcenter+0.1

—

+Fpeak–0.1

%

3rd.Pole frequency (In case of page 12)

Fcenter+0.1

—

+Fpeak–0.1

%

3rd.Pole frequency (In case of page 13)

F3rdpole

Fcenter–0.1

—

–Fpeak+0.1

%

Notes: 1. Regarding Fpeak+/–, F1stpole, F3rdpole higher frequency than Fcenter is specified to be positive (+ sign),

lower frequency than Fcenter is specified to be negative (– sign).

2. The above limitations of Fcenter, Fstep1, Fpeak+/–, Fstep2, F1stpole, F3rdpole, 1stPole, 2ndPole, 3rdPole,

and 4thPole are setting available vale.

Actual output clock is affected PLL jitter, above limitations are not guarantee value which is taken into

account the jitter and noise.

3. Minimum specification of modulation period is 1500 cycles, operation mode 4 needs over 2500 cycles.

Frequency Range Setting of Input Clock

FEST<2:0> pins need to set correspond to following table.

Table 1

Frequency Range Setting of Input Clock

Input Clock Frequency (MHz)

FSET<2>

FSET<1>

FSET<0>

28 to 60

H

L

L

60 to 80

H

L

H

80 to 100

H

H

L

Notes: 1. If MCLK frequency change under operating, it should need to start power on procedure again.

2. If FSET<2:0> setting are changed, reset function is needed again.

By the reset operation, all serial resisters are set to default settings, so it should set serial resister again.