AD9102BCPZ datasheet(2/43 Pages) AD

2 / 43 page

Data Sheet

AD9102

TABLE OF CONTENTS

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Rev. B | 2 of 43

Features................................................................ 1

Applications........................................................... 1

General Description...............................................1

Product Highlights................................................. 1

Functional Block Diagram......................................5

Specifications........................................................ 6

DC Specifications (3.3 V)................................... 6

DC Specifications (1.8 V)................................... 6

Digital Timing Specifications (3.3 V)...................7

Digital Timing Specifications (1.8 V)...................7

Input/Output Signal Specifications..................... 7

AC Specifications (3.3 V)................................... 8

AC Specifications (1.8 V)................................... 8

Power Supply Voltage Inputs and Power

Dissipation........................................................9

Absolute Maximum Ratings................................. 11

Thermal Resistance..........................................11

ESD Caution.....................................................11

Pin Configuration and Function Descriptions...... 12

Typical Performance Characteristics................... 14

Terminology......................................................... 19

Theory of Operation.............................................20

SPI Port ...........................................................20

DAC Transfer Function.....................................21

Setting IOUTFS, DAC Gain ................................21

Clock Input....................................................... 23

Generating Signal Patterns.............................. 23

DAC Input Datapaths....................................... 25

DOUT Function................................................ 25

Direct Digital Synthesizer (DDS)...................... 26

SRAM...............................................................26

Sawtooth Generator......................................... 27

Pseudorandom Signal Generator.....................27

DC Constant.....................................................28

Power Supply Notes.........................................28

Applications Information...................................... 29

Signal Generation Examples............................29

Waveform Generation Setups and Sample

Sequence....................................................... 30

SPI Control Register (SPICONFIG, Address

0x00).............................................................. 34

Power Status Register (POWERCONFIG,

Address 0x01)................................................ 34

Clock Control Register (CLOCKCONFIG,

Address 0x02)................................................ 35

Reference Resistor Register (REFADJ,

Address 0x03)................................................ 35

DAC Analog Gain Register (DACAGAIN,

Address 0x07)................................................ 35

DAC Analog Gain Range Register

(DACRANGE, Address 0x08).........................35

FSADJ Register (DACRSET, Address 0x0C)...36

Calibration Register (CALCONFIG, Address

0x0D)..............................................................36

Comp Offset Register (COMPOFFSET,

Address 0x0E)................................................36

Update Pattern Register (RAMUPDATE,

Address 0x1D)................................................37

Command/Status Register (PAT_STATUS,

Address 0x1E)................................................37

Command/Status Register (PAT_TYPE,

Address 0x1F)................................................ 37

Trigger Start to Real Pattern Delay Register

(PATTERN_DLY, Address 0x20).................... 37

DAC Digital Offset Register (DACDOF,

Address 0x25)................................................ 37

Wave Select Register (WAV_CONFIG,

Address 0x27)................................................ 38

DAC Time Control Register

(PAT_TIMEBASE, Address 0x28).................. 38

Pattern Period Register (PAT_PERIOD,

Address 0x29)................................................ 38

DAC Pattern Repeat Cycles Register

(DAC_PAT, Address 0x2B).............................39

TRIGGER Start to DOUT Signal Register

(DOUT_START, Address 0x2C)..................... 39

DOUT Configuration Register

(DOUT_CONFIG, Address 0x2D).................. 39

DAC Constant Value Register (DAC_CST,

Address 0x31)................................................ 39

DAC Digital Gain Register (DAC_DGAIN,

Address 0x35)................................................ 39

DAC Sawtooth Configuration Register

(SAW_CONFIG, Address 0x37).....................40

DDS Tuning Word MSB Register

(DDS_TW32, Address 0x3E)......................... 40

DDS Tuning Word LSB Register

(DDS_TW1, Address 0x3F)............................40

DDS Phase Offset Register (DDS_PW,

Address 0x43)................................................ 40

Pattern Control 1 Register (TRIG_TW_SEL,

Address 0x44)................................................ 40

Pattern Control 2 Register (DDS_CONFIG,

Address 0x45)................................................ 41

TW_RAM_CONFIG Register

(TW_RAM_CONFIG, Address 0x47)............. 41

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