AD9102BCPZ datasheet(21/43 Pages) AD

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Data Sheet

AD9102

THEORY OF OPERATION

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Rev. B | 21 of 43

Figure 31. Serial Register Interface Timing, MSB First Write, 4-Wire SPI

Configuration Register Update Procedure

Most SPI accessible registers are double buffered. An active regis-

ter set controls operation of the AD9102 during pattern generation,

while a set of shadow registers stores updated register values.

shadow registers. After SPI configuration update is complete, Bit

0 in RAMUPDATE (Register 0x1D) must be set to 1 to arm the

This is required regardless of the state of the pattern generator in

PAT_STATUS (Register 0x1E, Bit 1).

The RAMUPDATE applies to all SPI settings but does not apply

to the 4096 × 14-bit SRAM registers. Refer to the SRAM section

for the SRAM update procedure. Because of the double buffer

configuration, performing an SPI read operation returns the values

in the shadow registers, not the active registers.

DAC TRANSFER FUNCTION

The AD9102 DAC provides a differential current output: IOUTP/

IOUTN. Digital waveforms, generated on-chip for input to the DAC,

use a two's complement number system. The sign bit of each digital

waveform word is inverted immediately prior to input to each DAC

core. The DAC input code variable in Equation 1 and Equation 2

uses an offset binary number system (two's complement with the

sign bit inverted).

The DAC output current equations are as follows:

IOUTP = IOUTFS × DAC INPUT CODE/214

(1)

IOUTN = IOUTFS × ((214 − 1) − DAC INPUT CODE)/214

(2)

where:

DAC INPUT CODE = 0 to 214 − 1.

IOUTFS = 32 × IREF

(3)

IREF = VREFIO/RSET

(4)

When using on-chip RSET resistors, DAC gain accuracy can be im-

proved by employing the built-in automatic gain calibration feature

of the device (see the Automatic IOUTFS Calibration section).

Analog Current Outputs

Optimum linearity and noise performance of DAC outputs can be

achieved when they are connected differentially to an amplifier or a

transformer. In these configurations, common-mode signals at the

DAC outputs are rejected.

The output compliance voltage specifications listed in Table 1 and

Table 2 must be adhered to for the performance specifications in

those tables to be met.

SETTING IOUTFS, DAC GAIN

IOUTFS is the full-scale current or DAC gain. IREF is the current that

flows through the IREF resistor. The IREF resistor can be on or off

chip at the discretion of the user.

As expressed in Equation 3 and Equation 4, IOUTFS is a function of

the reference voltage at the REFIO terminal and RSET.

Voltage Reference

The AD9102 contains an internal 1.0 V nominal band gap refer-

ence, VBG. By default, the on-chip reference is powered up and

ready to be used. When using the on-chip reference, the REFIO

terminal needs to be decoupled to AGND using a 0.1 μF capacitor

as shown in Figure 32.

Alternatively, on-chip reference can be replaced by a more accurate

off-chip reference. To apply external reference, set REF_EXT in

POWERCONFIG (Register 0x01, Bit 4) to 1 then apply the external

reference to the REFIO pin. In this case, the 0.1 μF capacitor is not

required. The internal reference can be directly overridden by the

external reference.

When using an external reference, it is recommended to power

down the internal reference to lessen power consumption. To do so,

set REF_PDN field in POWERCONFIG (Register 0x01, Bit 5) to 1.

An external reference can provide tighter reference voltage toleran-

ces and/or lower temperature drift than the on-chip band gap. Table

13 summarizes reference connections and programming.

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