ADAU1361BCPZ-R7 datasheet(45/78 Pages) AD

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Data Sheet

ADAU1361

CONTROL REGISTERS

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Rev. E | 45 of 78

Table 28. PLL Control Register (Continued)

Byte

Bits

Bit Name

Description

…

11111111

65,535

[7:0]

N[15:8]

PLL numerator MSB. This value is concatenated with N[7:0] to make up a 16-bit number.

[7:0]

N[7:0]

PLL numerator LSB. This value is concatenated with N[15:8] to make up a 16-bit number.

N[15:8] (MSB)

N[7:0] (LSB)

Value of N

00000000

…

00000000

00001100

12 (default)

…

11111111

65,535

[6:3]

R[3:0]

PLL integer setting.

Setting

Value of R

0010

2 (default)

0011

0100

0101

0110

0111

1000

[2:1]

X[1:0]

PLL input clock divider.

Setting

Value of X

1 (default)

Type

Type of PLL. When set to integer mode, the values of M and N are ignored.

0 = integer (default).

1 = fractional.

Lock

PLL lock. This read-only bit is flagged when the PLL has finished locking.

0 = PLL unlocked (default).

1 = PLL locked.

PLLEN

PLL enable.

0 = PLL disabled (default).

1 = PLL enabled.

R2: Digital Microphone/Jack Detection Control, 16,392 (0x4008)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

JDDB[1:0]

JDFUNC[1:0]

Reserved

JDPOL

Table 29. Digital Microphone/Jack Detection Control Register

Bits

Bit Name

Description

[7:6]

JDDB[1:0]

Jack detect debounce time.

Setting

Debounce Time

5 mis (default)

10 ms

20 ms

40 ms

ADAU1361BCPZ-R7 Datasheet(PDF) 45 Page - Analog Devices

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