ADAU1361BCPZ-R7 datasheet(55/78 Pages) AD

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Data Sheet

ADAU1361

CONTROL REGISTERS

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Rev. E | 55 of 78

Table 43. Serial Port Control 1 Register (Continued)

Bits

Bit Name

Description

0 = left first (default).

1 = right first.

MSBP

MSB position in the LRCLK frame.

0 = MSB first (default).

1 = LSB first.

[1:0]

LRDEL[1:0]

Data delay from LRCLK edge (in BCLK units).

Setting

Delay (Bit Clock Cycles)

1 (default)

R17: Converter Control 0, 16,407 (0x4017)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reserved

DAPAIR[1:0]

DAOSR

ADOSR

CONVSR[2:0]

Table 44. Converter Control 0 Register

Bits

Bit Name

Description

[6:5]

DAPAIR[1:0]

On-chip DAC serial data selection in TDM mode.

Setting

Pair

First pair (default)

Second pair

Third pair

Fourth pair

DAOSR

DAC oversampling ratio. This bit cannot be set for 64× when CONVSR[2:0] is set to 96 kHz.

0 = 128× (default).

1 = 64×.

ADOSR

ADC oversampling ratio. This bit cannot be set for 64× when CONVSR[2:0] is set to 96 kHz.

0 = 128× (default).

1 = 64×.

[2:0]

CONVSR[2:0]

Converter sampling rate. The ADCs and DACs operate at the sampling rate set in this register. The converter rate selected is a ratio of

the base sampling rate, fS. The base sampling rate is determined by the operating frequency of the core clock. The serial port mirrors the

converter sampling rates set in this register.

Setting

Sampling Rate

Base Sampling Rate (fS = 48 kHz)

000

48 kHz, base (default)

001

fS/6

8 kHz

010

fS/4

12 kHz

011

fS/3

16 kHz

100

fS/2

24 kHz

101

fS/1.5

32 kHz

110

fS/0.5

96 kHz

111

Reserved

R18: Converter Control 1, 16,408 (0x4018)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reserved

ADPAIR[1:0]

ADAU1361BCPZ-R7 Datasheet(PDF) 55 Page - Analog Devices

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