AD8368 datasheet(16/20 Pages) AD

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AD8368

Data Sheet

Rev. C | Page 16 of 20

The choice of CDETO is a compromise of averaging time constant,

response time, and carrier leakage. If CDETO is selected to be too

small to speed up the response time, the AGC loop could start

tracking and leveling any amplitude envelope and corrupt the

constellation. Figure 38 illustrates a 16 QAM, 100 ksymbols per

second constellation with a degraded error vector magnitude

(EVM) of 5%. By increasing CDETO to 0.01 µF, the EVM is

improved to 1.1%.

REF –4.9dBm

CF 100MHz

SR 10kHz

CONST DIAG

MEAS SIGNAL

16 QAM

–1U

–1.31289U

262.578mU/

1.31289U

Figure 38. Degraded Error Vector Magnitude Performance for 16 QAM at

100 ksymbols per second (CDETO Too Small)

Figure 39 illustrates the measured EVM performance for a 16 QAM

modulation at 10 Msymbols per second using CDETO = 1 nF.

–40

–30

–20

–10

POWER IN (dBm)

Figure 39. Error Vector Magnitude Performance for

16 QAM 10 Msymbols per second

STABILITY AND LAYOUT CONSIDERATIONS

In some applications, the printed circuit board (PCB) parasitic, in

combination with the source impedance presented by the driving

stage, can present some troublesome impedance at high frequency

and can potentially unstablize the amplifier under certain extreme

conditions, such as high gain and high temperature. To avoid such

scenarios, it is recommended to include a simple parallel RL

snubbing network directly at the input terminal of the AD8368.

Figure 40 depicts an example of this network. The RL network

formed by R3 and L1 is used to minimize the negative impact

due to reflective source conditions at high RF frequencies and

ensures the amplifier operates unconditionally stable and

maintains the typical device performance.

On the underside of the chip scale package, there is an exposed

compressed paddle. This paddle is internally connected to the

ground of the chip. Solder the paddle to the low impedance ground

plane on the PCB to ensure specified electrical performance and to

provide thermal relief. It is also recommended that the ground

planes on all layers under the paddle be stitched together with

vias to reduce thermal impedance.

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