Data Sheet

AD8368

Rev. C | Page 17 of 20

EVALUATION BOARD

The standard evaluation board schematic and layout artwork is

presented in Figure 41 through Figure 44. The evaluation board

is fabricated on a multilayer FR-4 board, with 50 Ω-controlled

impedance transmission lines for the RF input and output traces.

The board is powered by a single supply in the 4.5 V to 5.5 V

range. The power supply is decoupled by 0.1 µF and 1 nF capacitors

at each power supply pin. Additional decoupling, in the form

of a series resistor or inductor at the supply pins, can also be added.

Table 6 details the various configuration options of the

evaluation board.

VPOS

VPOS1 VPOS2 VPOS3

ENBL

VPSI

VPSI

MODE

ICOM

INPT

OCOM

OUTP

VPSO

VPSO

VPSI

VPSI

AD8368

C20

1nF

C2

5.6pF

C11

1nF

C14

0.1µF

R11

0Ω

VPOS2

C12

1nF

C15

0.1µF

R12

0Ω

VPOS3

COUT

10nF OUTPUT

R31

OPEN

R32

OPEN

R30

OPEN

DET_IN

C1

OPEN

GAIN

C23

10nF

C4

1nF

C6

1nF

JP4

GAIN

C13

0.1µF

DET_OUT_TP

R35

OPEN

R3

215Ω

L1

10nH

CIN

10nF

INPUT

SW1

SW2

LOW

HI

ON

OFF

C10

1nF

R1

10kΩ

R2

10kΩ

ENABLE

R10

0Ω

VPOS1

Figure 40. Evaluation Board

Table 6. Evaluation Board Configuration Options

Component

Function

Default Conditions

R1, R2, R3, L1

Pull-Down Resistors for MODE and ENBL. RL network. Prevent potential instability impact

due to PCB parasitics and/or certain extreme conditions (see the Stability and Layout

Considerations section).

R1 = R2 = 10 kΩ

R3 = 215 Ω

L1 = 10 nH

R10, R11, R12,

C10, C11, C12,

C13, C14, C15

Supply Decoupling. Jumpers, power supply decoupling resistors, and filter capacitors.

R10 = R11 = R12 = 0 Ω

C10 = C11 = C12 = 1 nF

C13 = C14 = C15 = 0.1 µF

CIN

RF Input. CIN provides dc block for RF input.

CIN = 10 nF

COUT

RF Output. COUT provides dc block for RF output.

COUT = 10 nF

R31, R32

Feedback Path for AGC Operation. For a default setpoint of 63 mV rms, set R31 = 0 Ω and

remove R32. For other AGC setpoints, rms voltage = (1 + n) × 63 mV rms, where n = R31/R32.

R31 = R32 = Open

(VGA mode)

R35

Populate with 0 Ω to feed detector output RSSI voltage to DET_OUT_TP.

R35 = Open

C23

Sets the corner frequency of the output offset control loop high-pass filter.

C23 = 10 nF

C1, R30

Used for driving the detector externally. Set R30 to 50 Ω for matching. Set C1 to be a large

ac coupling capacitor.

C1 = Open

R30 = Open

C6

DETO Capacitor. Needs to be made larger for lower data rates (see the AGC Operation section).

C6 = 1 nF

C20, C2, C4

DECL Capacitor. Needs to be adjusted based on RF frequency in AGC operation (see the

AGC Operation section).

C20 = C4 = 1 nF

C2 = 5.6 pF

JP4

Jumper for AGC Mode of Operation. Provides feedback from the detector output to the

gain pin.

JP4 = not populated

(VGA mode)

SW1

Mode Switch. Low mode puts the part in gain-down mode. High mode puts the part in

gain-up mode. AGC operation requires gain-down mode.

SW1 = JP2

SW2

Power-Down. The part is disabled when the enable pin is tied to ground.

SW2 = JP3