TDA8779 datasheet(8/20 Pages) PHILIPS

8 / 20 page

1996 Sep 18

Philips Semiconductors

Objective speciﬁcation

10-bit converter interface (ADC/DAC) for

quadrature transceiver

TDA8779

ANALOG SIGNAL PROCESSING

Linearity

INLA

integral non linearity

ramp input; fCLK =20MHz

−±2

−

LSB

DNLA

differential non linearity

full-scale; ramp input;

fCLK =20MHz

−±0.5

−

LSB

50% full-scale; ramp input;

fCLK =20MHz

−±0.3

−

LSB

Noise ﬂoor; note 2

noise ﬂoor

fin = 5.1 MHz; 20 Msps

−−60

−

Harmonics; note 3

THD

total harmonic distortion

fi = 5.1 MHz; 20 Msps

−−54

−

Spurious free dynamic range

SFDR

spurious free dynamic range

fi = 5.1 MHz; 20 Msps

−

Matching between the I and Q channels

∆V

amplitude matching

fin = 5.1 MHz;

fCLK = 20 MHz;

Tamb =25°C

−−

∆ϕ

phase matching

fin = 5.1 MHz;

fCLK = 20 MHz;

Tamb =25°C

−−

Deg

Bandwidth

bandwidth maximum attenuation of

−0.3 dB

full-scale sine wave;

Tamb =25°C;

5.5

−−

MHz

50% full-scale sine wave;

Tamb =25°C;

tbf

−−

MHz

TIMING:(THE OUTPUT DATA IS AVAILABLE AFTER THE MAXIMUM DELAY TIME td); CL = 15 pF; see Fig.3

tds

sampling delay time

−−

5ns

output hold time

−−

output delay time

VCCO = 4.75 V

−

VCCO = 3.15 V

−

VCCO = 2.7 V

−

3-STATE OUTPUT DELAY TIMES; see Fig.4

tdZH

output delay enable HIGH

−

tdZL

output delay enable LOW

−

tdHZ

output delay disable HIGH

−

tdLZ

output delay disable LOW

−

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

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