38D5 datasheet(64/141 Pages) RENESAS

64 / 141 page

Rev.3.01

Aug 08, 2007

Page 64 of 134

REJ03B0158-0301

38D5 Group

Fig. 62 Clock generating circuit block diagram

System clock

Interrupt request

Interrupt disable flag I

Reset

WIT

instruction

STP instruction

XIN-XOUT

oscillation stop bit

CPUM BIT5

XIN

XOUT

XCOUT

XCIN

Timer 1 count source

selection bits

Port Xc switch bit

CPUM BIT4

“00”

“01”

“10”

“11”

Main clock division

ratio selection bit

CPUM BIT7, 6

On-chip oscillator

Internal system clock

selection bit

CPUM BIT3

1/2

Internal system clock selection bit

“0”

“1”

STP instruction

“1”

“0”

Timer 1

Timer 2

“01”

“00”

Frequency divider

for Timer

Timer 2 count source

selection bits

“00”

“10”

(2)

1/4

1/2

“0”

“1”

“0”

CPUM2 BIT0

On-chip oscillator stop bit

Main clock

divisio ratio

selection bit

Notes 1: When the XCIN-XCOUT oscillation is selected as the system clock, set the port Xc

switch bit to “1”.

2: Although a feed-back resistor exists on-chip, an external

feed-back resistor may be needed depending on conditions.

φSOURCE indicates the followings:

•XIN input in the frequency/2, 4, or 8 mode

•On-chip oscillator divided by 4 in the on-chip oscillator mode

•Sub-clock in the low-speed mode

However, when used as the A/D conversion clock by the A/D converter,

φSOURCE indicates the followings:

•XIN input in the frequency/2, 4, or 8 mode

•On-chip oscillator divided by 4 in the low-speed or the on-chip oscillator mode

φSOURCE

CPUM BIT6

(1)

(3)

38D5 Datasheet(PDF) 64 Page - Renesas Technology Corp

38D5 Datasheet(HTML) 64 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL