TDA9840 datasheet(14/28 Pages) PHILIPS

14 / 28 page

1998 Jul 03

Philips Semiconductors

Product speciﬁcation

TV and VTR stereo/dual sound processor

with digital identiﬁcation and I2C-bus control

TDA9840

I2C-BUS PROTOCOL FOR THE TV AND VTR

STEREO/DUAL SOUND PROCESSOR TDA9840

The TDA9840 has an I2C-bus interface with five registers:

status, test, switch, level and stereo adjustment register

controlled by a microcontroller via I2C-bus. The status

registers. The status byte represents the transmitter status

detected by the identification circuit and the power-on

reset status. The switch register controls the source

selectors of the AF signal part, and the level and stereo

adjustment register set the input level and stereo

adjustment stage. Additionally, a test register is built-in to

reduce the detection time of the identification circuit (test

mode, fast mode respectively).

I2C-bus transceiver and data-handling

(bus speciﬁcation)

The TDA9840 is controlled by a microcomputer via the

bidirectional 2-line I2C-bus. The two lines are a serial data

line (SDA) and a serial clock line (SCL). Both lines must be

connected to a positive supply via a pull-up resistor. Data

transfer may be initiated only when the bus is not busy.

When the bus is free, both lines are HIGH. The data on the

SDA line must be stable during the HIGH period of the

clock. The HIGH or LOW state of the data line can only

change, when the clock signal on the SCL line is LOW.

The set-up and hold times are specified in the

Chapter “Characteristics”.

A HIGH-to-LOW transition of the SDA line, while SCL is

HIGH, is defined as the start condition. A LOW-to-HIGH

transition of the SDA line, while SCL is HIGH, is defined as

the stop condition. The bus transceiver will be reset on the

reception of a start condition. The bus is considered to be

busy after the start condition. The bus is considered to be

free again after a stop condition.

Data format transmitter mode

For the data transmission no subaddress is to be

transmitted, because there is only one read register

implemented. So the total number of bytes reduces from

three to two. The second byte represents the status of

the IC.

Status register (see Table 4)

The bit D7 (PONRES) represents the status of the IC and

indicates whether the power-on reset was activated by

switching-on the supply voltage or a supply voltage

breakdown. If so, the I2C-bus transceiver, the digital PLLs

and integrators are initialized and the PONRES bit is set to

HIGH. After a successful reading of the status register, the

bit D7 will be reset to LOW.

The bits D5 and D6 represent the transmitter status

detected by the identification circuit (stereo, dual or mono

transmission). The other bits are set to 0 (default).

Data format for the receiver

Table 1

Registers for receiver mode (see Table 6)

The port register is without function, because this IC has

no control ports as TDA8415/6/7. A data byte for the

subaddress (01)HEX will not be stored in any register. An

acknowledge will be sent to the microcontroller.

The first byte of the data transmission is the slave address

and the second byte is the subaddress indicating the data

subaddress (00)HEX the n-th data byte will automatically be

stored under subaddress n

− 1.

All 8 bits of the subaddress are decoded by the device.

The subaddresses from (04)HEX to (FF)HEX are forbidden

for the user. If the I2C-bus transceiver receives

subaddresses from (05)HEX to (FF)HEX, no acknowledge

will be sent back to the microcontroller.

Switch register

The source selector is controlled by the switch register.

Table 7 shows the modes of operation. Note, that in the

event of the external operation mode, no further selection

is possible.

VALUE

Switch register

(00)HEX

Port register

(01)HEX (without function)

Level adjustment register

(02)HEX

Stereo adjustment register

(03)HEX

Test register

(04)HEX

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