TDA9840 datasheet(15/28 Pages) PHILIPS

15 / 28 page

1998 Jul 03

Philips Semiconductors

Product speciﬁcation

TV and VTR stereo/dual sound processor

with digital identiﬁcation and I2C-bus control

TDA9840

Level adjustment register

The information about the level adjustment of the AF

channel Vi 2 (pin 8) is stored in the level adjustment

the AF level adjustment stage. The level range is from

2.5 dB up to

−2.0 dB in 0.5 dB steps.

After a power-on reset, the data byte of the level

adjustment register will be set to (00)HEX: 0 dB gain at the

AF input Vi 2.

Stereo adjustment register

The information about the stereo adjustment of the

AF channel Vi 1 (pin 7) is stored in the stereo adjustment

the AF stereo adjustment stage. The stereo range is from

2.5 dB up to

−2.4 dB in 0.1 dB steps.

After a power-on reset, the data byte of the stereo

adjustment register will be set to (00)HEX: 0 dB gain at the

AF input Vi1.

Test register (also used for fast mode)

Table 12 shows the meaning of the test register. The

integration time of the integrator is approximately 1 s

(normal mode, default). If the data byte of this register is

set to HIGH, the integration time is reduced from

approximately 1 to approximately 0.5 s (fast mode, test

mode). The pull-in ranges of the identification PLLs are

changed to:

Stereo:

−0.89/+1.15 Hz

Dual:

±2.05 Hz.

If the integration time of the integrator is switched from one

mode to the other (i.e. from fast mode/test mode to normal

mode), the status register bits D5 and D6 might set to zero

internally (MONO). Therefore, the previous status register

information has to be stored by the microcontroller until the

transmitter status is detected again by the identification

circuit (now in the new mode) the first time.

The data byte of the test register can be reset in two

different ways to (00)HEX: integration time approximately

1 s, normal mode:

• after a power-on reset, for instance by switching the

power supply Vp off and on again

• data transmission via I2C-bus for the test register

(see Table 12).

Level and stereo adjustment

For the level and stereo adjustment of both AF channels

Vi1 and Vi2, the following procedure will be recommended.

Level adjustment of the AF channel V

• Feeds AF signal at the input V

i 2

• Sets the data byte of the switch register (dual mode)

to (1A)HEX

• Measures the signal at the outputs Vo2 or Vo4

• Adjusts the output level with the level adjustment

Stereo adjustment of the AF channel Vi 1

• Feeds AF stereo signals at the inputs Vi1 ((L+R)/2) and

Vi2 (R)

• Sets the data byte of the switch register (stereo mode)

to (2A)HEX

• Measures the crosstalk attenuation between Vo1 and

Vo2 or Vo3 and Vo4

• Adjusts the crosstalk attenuation with the stereo

adjustment register.

During the stereo adjustment the data byte of the level

adjustment register does not change.

After the level and stereo adjustment, the bytes of the level

and stereo adjustment register must be stored by the

microcontroller in a memory. (To avoid mis-adjustment it

would be wise to compare the stored bytes with the proper

adjustment bytes). If the PONRES bit of the status register

will be set to HIGH (see status register) the data bytes for

these both registers must be sent out of the memory to the

TDA9840 via I2C-bus. Also the data byte of the switch

AF outputs are muted.

TDA9840 Datasheet(PDF) 15 Page - NXP Semiconductors

TDA9840 Datasheet(HTML) 15 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

Datasheet Download

Link URL