LTC6362 datasheet(11/42 Pages) AD

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LTC6363 Family

Rev. C

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Note 1: Stresses beyond those listed under Absolute Maximum Ratings may

cause permanent damage to the device. Exposure to any Absolute Maximum

Rating condition for extended periods may affect device reliability and lifetime.

Note 2: Absolute Maximum input voltage for the LTC6363-0.5/LTC6363-1/

LTC6363-2 is conservatively calculated assuming the worst case output

voltage. For details on this calculation refer to the Input Pin Protection section.

Note 3: In the LTC6363, if input pins (+IN, –IN, VOCM and SHDN) must

exceed either supply voltage, the input current must be limited to less than

10mA. Additionally, if the differential input voltage exceeds 1.4V, the input

current must be limited to less than 10mA. In the LTC6363-0.5/LTC6363-1/

LTC6363-2 versions, the same limits apply to VOCM, SHDN and the internal

amplifier’s inputs. Please see the Input Common Mode Voltage Range and

Input Pin Protection sections for additional details on calculating the input

voltages on the internal amplifier’s inputs while in a feedback configuration.

Note 4: A heat sink may be required to keep the junction temperature below

the absolute maximum rating when the output is shorted indefinitely.

Note 5: The LTC6363I and LTC6363I-0.5/LTC6363I-1/LTC6363I-2 are

guaranteed functional over the operating temperature range of –40°C

to 85°C. The LTC6363H and LTC6363H-0.5/LTC6363H-1/LTC6363H-2

are guaranteed functional over the operating temperature range of

–40°C to 125°C.

Note 6: The LTC6363I and LTC6363I-0.5/LTC6363I-1/LTC6363I-2 are

guaranteed to meet specified performance from –40°C to 85°C. The

LTC6363H and LTC6363H-0.5/LTC6363H-1/LTC6363H-2 are guaranteed

to meet specified performance from –40°C to 125°C.

Note 7: Differential offset voltage, differential offset voltage drift, and

PSRR are referred to the internal amplifier’s input (summing junction)

to allow for direct comparison of gain blocks with discrete amplifiers.

CMRRI, CMRRIO and voltage noise are referenced to the LTC6363-0.5,

LTC6363-1 and LTC6363-2's input pins. Refer to the Test Circuits section

for more details.

Note 8: Maximum differential offset voltage drift, input offset current drift

and differential gain drift are determined by sampling typical parts. Drift is

not guaranteed by test or QA sampled at this value.

Note 9: Input common mode range is tested by verifying that at the limits

stated in the Electrical Characteristics table, the differential offset (VOSDIFF)

and common mode offset (VOSCM) have not deviated by more than

±200µV and ±10mV respectively compared to the VICM = 5V (at VS = 10V),

VICM = 2.5V (at VS = 5V) and VICM = 1.5V (at VS = 3V) cases.

Output common mode range is tested by verifying that at the limits stated

in the Electrical Characteristics table, the common mode offset (VOSCM) has

not deviated by more than ±15mV compared to the VOCM = 5V (at VS = 10V),

VOCM = 2.5V (at VS = 5V) and VOCM = 1.5V (at VS = 3V) cases.

Note 10: Input bias current is defined as the average of the input currents

flowing into the input pins (–IN and +IN). Input Offset current is defined as

the difference between the input bias currents (IOS = IB+ – IB–).

Note 11: Full power bandwidth is calculated from the slew rate.

FPBW = SR/(2 • π • VP)

ELECTRICAL CHARACTERISTICS

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