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PS12

Functional Description

The PS12 provides power-up and power-down sequencing

for devices such as power supply modules, load switches,

ICs, etc. The four outputs PSA thru PSD are configured with

open drain drivers, which are typically used to power supply

modules. Some systems may require level-shifting or isolat-

ing drivers.

Upon application of power, the power-up delay timer is reset

and the enable outputs PSA thru PSD are de-asserted.

Window Comparator

The state of the four PS outputs and the associated power-

up and power-down sequencing is controlled by a window

comparator formed by the ON and OV voltage compara-

tors.

These comparators define a voltage window having thresh-

olds programmed by an external resistive divider. The ON

comparator defines the lower threshold of the window, while

the OV comparator defines the upper threshold of the win-

dow. Both comparator thresholds feature 200mV hyster-

esis.

Power-up and Power-down Sequence

Power supply voltage moving into the window causes the

start of a power-up sequence. The sequence consists of the

power-up delay, programmed by C

assertion of the PS outputs in the sequence ABCD using the

enable to enable delays (T

the resistors (R

Power supply voltage moving outside the window causes

the start of a power-down sequence. The sequence consists

of the de-assertion of the most recently asserted PS out-

put, typically PSD, and subsequent de-assertion of other as-

serted PS outputs in the sequence DCBA using the enable

delays (T

R

The power-up sequence may be terminated prematurely

by a power-down sequence. On the other hand, the pow-

er-down sequence is latching in nature; once power-down

is initiated, the sequence is brought to completion regard-

less of changes in the state of the window comparator. After

the power-down sequence is completed, a new power-up

sequence may start, depending on the state of the window

comparator at that time.

Enable Outputs at Low V

IN

The internal circuits of the PS12 can be expected to provide

well-defined outputs at a power supply voltage of about 3.3V

and above.

At lower power supply voltages, the existence of poorly

defined output levels should typically not be an issue if the

PS12 and the controlled loads share the same supply, since

the loads may not be adequately biased as well.

Some caution is warranted when the controlled loads are

independently powered and the power supply voltage to the

PS12 is inadequate or ill-defined.

Delay Time Considerations

The PS12 is characterized for enable to enable delay times

between 5ms and 200ms, which should cover most applica-

tions. Initial characterization of this device shows excellent

linearity between delay time and programming resistance for

a delay time in the range of 2.5ms to 5 seconds.

Shorting of a programming pin is not advised, and may re-

duce long term reliability, as internal circuits are not dimen-

sioned for sourcing the resultant pin current.

Power-up Delay (PUD)

The power-up delay is set by the time required to charge

the C

of 12μA, resulting in a delay time of 100ms per µF. Charging

continues past the power-up delay until a voltage of about

4V is reached.

An internal voltage comparator at the PUD pin inhibits the

power-up sequence, should the C

charged before initiating the power-up delay.

Discharge of the C

down sequence. The discharge transistor is turned on at the

end of the sequence when PSA is the last remaining as-

serted output.